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february 2004 intel ? IXP2400 network processor datasheet product features the intel ? IXP2400 network processor enables faster deployment of intelligent network services by providing high programming flexibility, code re-use, and high-performance processing. IXP2400 network processor supports a wide variety of wan and lan applications requiring support for a broad range of speeds, currently ranging from oc-3 to oc-48. high performance and scalability is achieved through an inno vative microengine architecture that includes a multi-threaded distribution cache architecture that enables pipeline features in software. the microengin es feature innovative inter-thread communication capabilities for efficient processing at high line rates, and general-purpose hardware elements that support advanced networking algorithms. the microengines play a key role in the intel ? exchange architecture (ixa) store and forward ar chitecture, providing flexible, rich network processing in converged communications environments. eight integrated microengine version 2 processors ? operating frequencies of 400 and 600 mhz ? configurable to four or eight threads per microengine ? 640 x 32-bit local memory per microengine ? sixteen-entry cam per microengine with single cycle lookup ? next neighbor bus: a dedicated datapath between adjacent microengines ? crc unit per microengine supporting crc-16 (ccitt) and crc-32 ? 4k-instruction control store per microengine ? support for generalized thread signaling ? reflector access to read or write data between any microengines integrated intel xscale core ? operating frequencies of 400 and 600 mhz ? high-performance, low-power, 32-bit embedded risc processor ? 32-kbyte instruction cache ? 32-kbyte data cache ? 2-kbyte mini data cache two uni-directional 32-bit low-voltage transistor-transistor logic (lvttl) data interfaces ? speeds from 25 to 133 mhz supported ? separately configurable for pos-phy, utopia 1/2/3, or csix-l1-b protocol support ? interprocessor ?cbus? communication industry-standard pci bus version 2.2 interface for 64-bit, 66-mhz i/o industry-standard double-data-rate (ddr) sdram memory interface ? peak bandwidth of 2.4 gb/s ? clock speeds of 100, 150 mhz supported when IXP2400 is running at 600 mhz; 100 mhz when IXP2400 is running at 400 mhz ? error correction code (ecc) ? addressable from the intel xscale core, mes, and pci two industry-standard 32-bit quad-data-rate (qdr) sram interfaces ? peak bandwidth of 1.6 gb/s per channel ? 100- or 133-mhz sram when IXP2400 is running at 400 mhz; 100-, 150- or 200-mhz sram when IXP2400 is running at 600 mhz ? hardware support for linked list and ring operations ? atomic bit operations ? atomic arithmetic support ? addressable from the intel xscale core, mes, and pci additional integrated features ? hardware hash unit (48, 64 and 128 bit) ? 16-kbyte scratchpad memory ? serial port for debug ? eight general-purpose i/o pins ? four 32-bit timers 1356-ball fcbga2 package ? dimensions of 37.5 mm x 37.5 mm ? 1 mm solder ball pitch notice: please verify with your local intel sales office that you have the latest datasheet before finalizing a design. document number: 301164-011
intel ? IXP2400 network processor 2 datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the IXP2400 network processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2003 bunnypeople, celeron, chips, dialogic, etherexpress, etox, flashfile, i386, i486, i960, icomp, instantip, intel, intel centrino , intel centrino logo, intel logo, intel386, intel486, intel740, inteldx2, inteldx4, in telsx2, intel inside, intel inside logo, intel netburst, intel netmerge, intel netstructure, intel singledriver, intel speedstep, intel strataflash, intel xe on, intel xscale, iplink, itanium, mcs, mmx, mmx logo, optimize r logo, overdrive, paragon, pdcharm, pentium, pentium ii xeon, pentium iii xeon, performance at your command, sound mark, the computer inside., th e journey inside, vtune, and xircom are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. revision history date revision description january 2002 001 release for the customer information book v0.3. march 2002 002 initial release of advance information for intel ? field personnel and customers under nda. june 2002 003 release for the customer information book v0.4. july 2002 004 update to best-known advance information for intel ? field personnel and customers under nda. september 2002 005 further updates (primarily to electr ical specifications) to advance information for intel ? field personnel and customers under nda. november 2002 006 further updates to signal and electrical information; advance information for intel ? field personnel and customers under nda. december 2002 007 further updates, mostly to electrical information; advance information for intel ? field personnel and customers under nda. march 2003 008 updated electrical specifications with b stepping information; advance information for intel ? field personnel and customers under nda. april 2003 009 added media switch fabric mode signal-usage tables, ball map; updated electrical specifications. october 2003 010 minor modifications to figures 10, 11, and 45. february 2004 011 further modifications to figur es 10 and 11; changes to tables 6, 30, and 53.
intel ? IXP2400 network processor datasheet 3 contents 1.0 product description ......................................................................................................... ..7 2.0 functional units............................................................................................................ ...10 2.1 functional overview........................................................................................... 10 2.2 intel xscale ? core.............................................................................................. 11 2.2.1 instruction cache .................................................................................. 12 2.2.2 data cache ........................................................................................... 12 2.2.3 debug.................................................................................................... 12 2.2.4 memory management ........................................................................... 13 2.2.5 branch target buffer ............................................................................. 13 2.3 microengines ...................................................................................................... 13 2.3.1 control store ......................................................................................... 14 2.3.2 general-purpose registers (gprs) ...................................................... 15 2.3.3 transfer registers ................................................................................. 15 2.3.4 next neighbor registers ....................................................................... 15 2.3.5 local memory (lm) ............................................................................... 15 2.3.6 crc unit ............................................................................................... 16 2.3.7 event signals ........................................................................................ 16 2.4 ddr sdram...................................................................................................... 16 2.5 sram ................................................................................................................. 17 2.5.1 sram controller configurations ........................................................... 18 2.6 media and switch fabric interface ..................................................................... 19 2.6.1 phy modes supported.......................................................................... 19 2.6.2 csix ...................................................................................................... 20 2.7 pci controller..................................................................................................... 20 2.8 xpi unit .............................................................................................................. 21 2.8.1 gpio ..................................................................................................... 21 2.8.2 serial port.............................................................................................. 21 2.8.3 slowport ................................................................................................ 21 3.0 signal description .......................................................................................................... .23 3.1 ballout functional groupings diagram............................................................... 23 3.2 ball descriptions grouped by function .............................................................. 23 3.2.1 ddr sdram......................................................................................... 24 3.2.2 sram .................................................................................................... 24 3.2.3 media and switch fabric (msf) interface ............................................. 25 3.2.4 pci ........................................................................................................ 63 3.2.5 slowport signals ................................................................................... 64 3.2.6 gpio signals......................................................................................... 64 3.2.7 serial port signals................................................................................. 65 3.2.8 clock signals......................................................................................... 65 3.2.9 test, jtag, and miscellaneous signals................................................ 65 3.2.10 configuration pins ................................................................................. 67 3.2.11 pin state during reset.......................................................................... 68 3.3 power supply sequencing ................................................................................. 68 3.3.1 power-up sequence ............................................................................. 68 3.3.2 power-down sequence......................................................................... 68
intel ? IXP2400 network processor 4 datasheet 3.3.3 slowport clock behavior during reset................................................. 69 3.3.4 pullup/pulldown and unused pin guidelines ........................................ 69 3.4 ball information .................................................................................................. 70 3.5 ball list tables................................................................................................... 72 3.5.1 balls listed in alphanumeric order by signal name............................. 72 3.5.2 balls listed in alphanumeric order by ball location............................. 85 4.0 electrical specifications .................................................................................................. 9 8 4.1 absolute maximum ratings ............................................................................... 98 4.1.1 reducing power consumption............................................................ 100 4.2 ac/dc specifications....................................................................................... 101 4.2.1 clock timing specifications ................................................................ 101 4.2.2 pci i/o unit ......................................................................................... 101 4.2.3 sram.................................................................................................. 105 4.2.4 ddr sdram ...................................................................................... 107 4.2.5 media and switch fabric (msf) interface ........................................... 114 4.2.6 cbus ................................................................................................... 117 4.2.7 slowport, gpio, and serial i/o buffer ................................................ 118 4.2.8 jtag ................................................................................................... 121 5.0 mechanical specifications............................................................................................. 124 5.1 package dimensions ....................................................................................... 124 figures 1 IXP2400 network processor oc-48 line card...................................................7 2 IXP2400 network processor functional signal groups diagram 1 ....................8 3 IXP2400 network processor functional signal groups diagram 2 ....................9 4 IXP2400 network processor chassis concept block diagram ........................10 5 intel xscale ? core internal block diagram .......................................................12 6 microengine block diagram ..............................................................................14 7 clock configuration...........................................................................................18 8 example slowport connection..........................................................................22 9 high-level overview of ballout functional groupings diagram (ball side) ........................................................23 10 IXP2400 network processor ball map (bottom left side) ..................................70 11 IXP2400 network processor ball map (bottom right side) ................................71 12 pll power supply connection .......................................................................100 13 sys_clk timing ............................................................................................101 14 pci clock signal ac parameter measurements.............................................103 15 pci bus signals ..............................................................................................104 16 qdr load circuit ............................................................................................106 17 qdrii timing reference.................................................................................107 18 data and error correction setup/hold relationship to/from data strobe (read operation) ........................................................................109 19 data and error correction valid before and after data strobe (write operation) .................................................................................110 20 write preamble duration.................................................................................110 21 write postamble duration ...............................................................................110 22 command signals valid before and after clock rising edge ........................110 23 clock enable valid before and after clock rising edge ................................111
intel ? IXP2400 network processor datasheet 5 24 chip select valid before and after clock rising edge ...................................111 25 clock cycle time ............................................................................................111 26 skew between any system memory differential clock pair...........................111 27 clock high time ..............................................................................................112 28 clock low time...............................................................................................112 29 data strobe falling edge output access time to clock rising edge ............112 30 data strobe falling edge output access time from clock rising edge ........112 31 clock rising edge output access time to the first data strobe rising edge.................................................................................113 32 clock rising edge output access time to the data strobe preamble falling edge ........................................................................113 33 clock rising edge output access time to output clock falling edge ..........................................................................................113 34 input clock falling edge setup time to the first data strobe rising edge .........................................................................................114 35 input clock rising edge hold time from the first data strobe rising edge .........................................................................................114 36 input clock falling edge hold time from the data strobe preamble falling edge ........................................................................114 37 media clock timing.........................................................................................115 38 receive utopia/pos/csix ...........................................................................117 39 transmit utopia/pos/csix ..........................................................................117 40 mode 0 single write transfer for self-timing device ? slowport .................119 41 mode 0 single read transfer for self-timing device ? slowport .................120 42 boundary scan general timing ......................................................................121 43 boundary scan tristate timing .......................................................................122 44 boundary scan reset timing..........................................................................122 45 IXP2400 network processor general mechanical drawing ............................124 tables 1 ddr supported configurations.......................................................................... 17 2 sram controller configurations ........................................................................ 19 3 total memory per channel................................................................................. 19 4 ddr sdram signals......................................................................................... 24 5 sram signals .................................................................................................... 25 6 msf data signals .............................................................................................. 26 7 1x32 sphy utopia/pos-phy master mode ................................................... 28 8 2x16 sphy utopia/pos master mode............................................................ 30 9 4x8 sphy utopia/pos-phy master mode ..................................................... 32 10 1x16+2x8 sphy utopia/pos master mode .................................................... 34 11 x32 utopia level 3 mphy mode ..................................................................... 37 12 x32 pos-phy level 3 mphy mode .................................................................. 39 13 1x32 csix mode ................................................................................................ 41 14 x16 utopia level 2 mphy-32 + x16 sphy (utopia or pos-phy) mode ............................................................................ 44 15 x16 utopia level 2 mphy-32 + 2x8 sphy (utopia or pos-phy) mode ............................................................................ 46 16 x16 pos-phy level 2 mphy-32 + x16 sphy (utopia or pos-phy) mode ............................................................................ 49 17 x16 pos-phy level 2 mphy-32 + 2x8 sphy (utopia or pos-phy) mode ............................................................................ 51
intel ? IXP2400 network processor 6 datasheet 18 1x32 sphy slave mode..................................................................................... 54 19 2x16 sphy slave mode..................................................................................... 56 20 4x8 sphy slave mode....................................................................................... 58 21 1x16+2x8 sphy slave mode............................................................................. 60 22 cbus pinout ....................................................................................................... 62 23 pci signals ........................................................................................................ 63 24 slowport signals ................................................................................................ 64 25 gpio signals ..................................................................................................... 65 26 serial port signals.............................................................................................. 65 27 clock signals ..................................................................................................... 65 28 test, jtag, and miscellaneous signals ............................................................ 66 29 configuration/gpio pins.................................................................................... 67 30 IXP2400 network processor signal-type abbreviations ................................... 72 31 ball list in alphanumeric order by signal location ........................................... 72 32 ball list in alphanumeric order by ball location ............................................... 85 33 functional operating temperature range......................................................... 98 34 functional operating voltage range ................................................................. 99 35 power totals for b stepping .............................................................................. 99 36 maximum power for thermal solution ............................................................... 99 37 maximum power consumption by power supply ............................................ 100 38 sys_clk dc specification ............................................................................. 101 39 sys_clk ac specifications............................................................................ 101 40 absolute maximum pci ratings ...................................................................... 102 41 pci typical and maximum power .................................................................... 102 42 pci dc specifications...................................................................................... 102 43 overshoot/undershoot specifications.............................................................. 103 44 66-mhz pci clock signal ac parameters ....................................................... 103 45 33-mhz pci clock signal ac parameters ....................................................... 104 46 33-mhz pci signal timing............................................................................... 104 47 66-mhz pci signal timing............................................................................... 105 48 qdr dc specifications.................................................................................... 105 49 qdr and qdrii signal timing parameters..................................................... 106 50 ddr sdram dc parameters for 100/150 mhz .............................................. 107 51 ddr sdram ac parameters for 100/150 mhz .............................................. 108 52 msf (lvttl) dc thresholds .......................................................................... 115 53 msf overshoot/undershoot specifications ..................................................... 115 54 media clock dc specification.......................................................................... 115 55 media clock ac specifications ........................................................................ 116 56 media interface signal ac parameters............................................................ 116 57 cbus (lvttl) driver dc specifications .......................................................... 117 58 slowport, gpio, and serial i/o buffer ac/dc specifications.......................... 118 59 slowport write timing...................................................................................... 119 60 slowport read timing ..................................................................................... 120 61 jtag dc specifications................................................................................... 121 62 jtag ac specifications................................................................................... 122 63 IXP2400 network processor package dimensions ......................................... 124 64 IXP2400 network processor die size.............................................................. 125
intel ? IXP2400 network processor datasheet 7 1.0 product description the intel ? IXP2400 network processor is a second-generation high-performance device . the IXP2400 is a highly integrated, programmable data processor that provides high-performance parallel processing power and flexibility to a wide variety of oc-48 (2.5 gb/s) networking, communications, and data-intensive applications. the IXP2400 has a store and forward architecture that comb ines a state-of-the-art intel xscale core with eight multithreaded, independent 32-bit risc data engines that, when combined, can provide a total of 5.4 giga-operations per second. figure 1 shows two IXP2400 network processors in a typical 2.5 gb/s full-duplex line rate application. figure 2 and figure 3 illustrate the functional signal groups within the IXP2400. figure 1. IXP2400 network processor oc-48 line card a9806-02 switch fabric gasket ingress processor sar'ing classification metering policing initial congestion management egress processor traffic shaping flexible choices diff serve tm 4.1 ... intel ? IXP2400 ingress processor intel ? IXP2400 egress processor host cpu (iop or ia) intel ? ixf6048 framer oc48 oc48 oc48 oc48 q d r q d r s d r a m q d r q d r s d r a m ddr sdram qdr sram queues & table qdr sram queues & tables 1x oc-48 or 4x oc-12 ddr sdram
intel ? IXP2400 network processor 8 datasheet figure 2. IXP2400 network processor functional signal groups diagram 1 a9808-02 intel ? IXP2400 network processor vcc1.5 vcc vss vssa vcc2.5 power supplies txcsrb txcfc txcpar txcsof txcdata[3:0] rxcsrb rxcfc rxcpar rxcsof rxcdata[3:0] media switch fabric interface flow- control d_ck_l[2:0] d_dq[63:0] d_cs_l[1:0] rxsof(n) d_rcvenout_l d_ba[1:0] d_dm[8:0] d_we_l d_ecc[7:0] d_cas_l d_ras_l d_ck[2:0] d_dqs[8:0] d_a[13:0] d_cke[1:0] r_rcvenin_l d_rcomp[1:0] d_vref[1:0] ddram interface rxclk23 rxenb(n) rxval(n) txaddr[3:0] rxeof(n) rxprty(n) rxerr(n) txclk23 txenb(n) txsof(n) txeof(n) txerr(n) rxclk01 rxdata[31:0] rxaddr[3:0] rxpfa media switch fabric interface pci_par64 pci_par txpfa txsfa txpadl[1:0] txfa(n) pci_frame_l pci_idsel pci_stop_l pci_irdy_l pci_req64_l rxfa(n) pci_trdy_l pci_devsel_l general- purpose i/o pci_ad[63:0] gpio[7:0] serial port serial_rx serial_tx pci_cbe_l[7:0] vcca pci_ack64_l vcc3.3 pci_perr_l pci_serr_l pci_req_l[0] pci_req_l[1] pci_grant_l[0] pci_intb_l pci_rst_l pci_clk pci_rcomp pci_grant_l[1] pci_inta_l pci interface rxpadl[1:0} rxrcomp msf_clk_bypass txrcomp txdata[31:0] txclk01 txprty(n) sn_k_l[1:0] sn_c[1:0] sn_c_l[1:0] sn_bwe_l[1:0] sn_rpe_l[1:0] sn_do[15:0] sn_pi[15:0] sn_di[15:0] sn_cin_l[1:0] sn_cin[1:0] sn_k[1:0] sn_po[1:0] sn_wpe_l[1:0] sn_a[23:0] sn_vref sn_zq[1:0] qdram interface two of these. "n" = 1 or 0
intel ? IXP2400 network processor datasheet 9 figure 3. IXP2400 network processor functional signal groups diagram 2 a9810-02 intel ? IXP2400 network processor sys_reset_l sys_clk t_load t_diag_clk trst_l tdi_t_scan_en tms_t_clk tck sys_reset_out_l t_sys_refclk thermda thermdc pll_div_bypass pll_bypass ieee 1149.1 and test signals clock signals sp_rd_l slow port interface sp_ad[7:0] sp_ack_l sp_cs_l[1:0] sp_wr_l sp_dir_sp_a[1] sp_oe_l sp_ale_l sp_cp_sp_a[0] sp_clk
intel ? IXP2400 network processor 10 datasheet 2.0 functional units 2.1 functional overview this section provides a brief overview of the IXP2400 network processor internal hardware. figure 4 is a simple block diagram that shows the device?s major internal blocks. the major blocks are: intel xscale core ? general-purpose 32-bit ri sc processor compatible to arm version 5 architecture. the intel xscale core is used to initialize and manage the chip, and can be used for higher layer network processing tasks. microengines (mes) ? 8 32-bit programmable engines specialized for network processing. microengines do the main data plane processing per packet. dram controller ? 1 ddr sdram controller. typically dram is used for data buffer storage. sram controller ? 2 independent controllers for qdr sram. typically sram is used for control information storage. scratchpad memory ? 16 kbytes of storage for general-purpose use. media and switch fabric interface (msf) ? interface for network framers and/or switch fabric. contains receive and transmit buffers. hash unit ? polynomial hash accelerator. the in tel xscale core and microengines can use it to offload hash calculations. pci controller ? 64-bit pci rev 2.2 compliant io bus. pci can be used to either connect to a host processor, or to attach pci-compliant peripheral devices. figure 4. IXP2400 network processor chassis concept block diagram a9811-01 media switch fabric (msf) scratchpad memory sram controller 0 sram controller 1 dram controller hash unit pci controller cap me cluster 0 me 0x1 me 0x0 me 0x2 me 0x3 me cluster 1 me 0x10 me 0x11 me 0x13 me 0x12 intel xscale? core peripherals (xpi) intel xscale? core performance monitor
intel ? IXP2400 network processor datasheet 11 cap ? chip-wide control and status register s. these provide special inter-processor communication features to allow flexible and efficient inter-microengine and microengine-to-intel-xscale-core communication. intel xscale ? core peripherals (xpi) ? interrupt controller, timers, uart, general-purpose io (gpio) and interface to low-speed off chip peripherals (such as maintenance port of network devices) and flash memory. performance monitor ? counters that can be programmed to count selected internal chip hardware events; can be used to analyze and tune performance. 2.2 intel xscale ? core the intel xscale core is a 32-bit general-purpose ri sc processor. it incorporates an extensive list of architecture features that al lows it to achieve high performance. the intel xscale core is compatible to arm* version 5 (v5) architecture. it implements the integer instruction set of arm v5, but does not provide hardware support of the floating point instructions. the intel xscale core provides the thumb instruction set (arm v5t) and the arm v5e dsp extensions. backward compatibility with the first generation of strongarm* products is maintained for user-mode applications. operating systems may require modifications to match the specific hardware features of the intel xscale co re and to take advantage of the performance enhancements to the core. figure 5 shows the major functional intel xscale core blocks that surround the arm* v5te core. the following sections give a brief, high-level overview of these blocks.
intel ? IXP2400 network processor 12 datasheet 2.2.1 instruction cache the intel xscale core implements a 32-kbyte, 32- way set associative instruction cache with a line size of 32 bytes. all requests that ?miss? the instruction cache generate a 32-byte read request to external memory. a mechanism to lock critical code within the cache is also provided. 2.2.2 data cache the intel xscale core implements a 32-kbyte 32-way set-associative data cache, and a 2-kbyte 2-way set-associative mini-data cache. each cache has a line size of 32 bytes and supports write-through or write-back cachi ng. the data/mini-data cache is controlled by the page attributes defined in the memory management unit (mmu) architecture. 2.2.3 debug the intel xscale core supports software debugging, via the jtag port, through two instruction address breakpoint registers, one data-address breakpoint register, one data-address/mask breakpoint register, and a trace buffer. figure 5. intel xscale ? core internal block diagram a9812-01 instruction cache 32 kbytes 32 ways lockable by line mini-data cache 2 kbytes 2 ways performance monitoring debug hardware breakpoints branch history table branch target cache 128 entry co-processor single cycle throughput (16*32) 16-bit simd 40-bit accumulator jtag power management write buffer 8 entries full coalescing intel ? arm* version 5te core i-mmu 32 entry tlb fully associative lockable by entry d-mmu 32 entry tlb fully associative lockable by entry fill buffer 4 - 8 entries data cache max 32 kbytes 32 ways wr-back or wr-through hit and miss data ram max 28 kbytes re-map of data cache idle / drowsy / sleep * arm and strongarm are registered trademarks of arm, ltd.
intel ? IXP2400 network processor datasheet 13 2.2.4 memory management the intel xscale core implemen ts the memory management un it (mmu) architecture specified in the arm architecture reference manual. th e mmu provides access protection and virtual to physical address translation. the mmu architect ure also specifies the caching policies for the instruction cache and data memory. these policies are specified as page attributes and include: identifying code as cacheable or non-cacheable selecting between the mini-data cache or data cache write-back or write-through data caching enabling data write allocation policy enabling the write buffer to coalesce stores to external memory 2.2.5 branch target buffer the intel xscale core provides a branch targ et buffer (btb) to predict the outcome of branch-type instructions. it provides storage for th e target address of branch-type instructions and predicts the next address to present to the instru ction cache when the curren t instruction address is that of a branch. the btb holds 128 entries. 2.3 microengines the microengines (mes) do most of the progra mmable per-packet processing in the IXP2400. there are eight mes, connected as shown in figure 4 . the mes have access to all shared resources (sram, dram, msf, etc.) as well as pr ivate connections between adjacent mes. the mes provide support for software-controlled multi-threaded operation. given the disparity in processor cycle times versus external memory times, a single thread of execution will often block, waiting for external memory operations to complete. having multiple threads available allows for threads to interleave operation; there is often at least one thread ready to run while others are blocked.
intel ? IXP2400 network processor 14 datasheet 2.3.1 control store the control store is a ram, which holds the program that the me executes. it holds 4096 instructions, each of which is 40 bits wide. it is initialized by an external device (for example, the internal intel xscale core.) the control store can optionally be protected by parity against soft errors. figure 6. microengine block diagram a9813-01 128 gprs (a bank) d e c o d e 128 gprs (b bank) 128 next neighbor 128 d xfer out 128 d xfer in nn_data_in d_push s_push 128 s xfer in 640 local mem a_src b_src immed nn_data_out dest control store lm_addr_1 lm_addr_0 crc_remainder a_operand b_operand alu_out s_push s_pull d_pull crc unit local csrs t_index nn_get execution datapath (shift, add, subtract, multiply logicals, find first bit, cam) 128 s xfer out control data
intel ? IXP2400 network processor datasheet 15 2.3.1.1 microengine contexts there are eight hardware contexts available in the me. to allow for efficient context swapping, each context has its own register set, program counter, and context-specific local registers. having a copy per context eliminates the need to mo ve context-specific information to/from shared memory and me registers for each context swap. fast context swapping allows a context to do computation while other contexts wait for io (typi cally external memory accesses) to complete or for a signal from another context or hardware unit. 2.3.2 general-purpose registers (gprs) the gprs are used for general programming purposes. they are read and written exclusively under program control. gprs, when used as a source in an instruction, supply operands to the execution datapath. when used as a destination in an instruction, they are written with the result of the execution datapath. the specific gprs selected are encoded in the instruction. the gprs are physically and logically contained in two banks, gpr a and gpr b. 2.3.3 transfer registers transfer registers (xfer registers) are used for tr ansferring data to and from the me and locations external to the me, (for example drams, srams etc). there are four types of transfer registers: 1. s_transfer_in 2. s_transfer_out 3. d_transfer_in 4. d_transfer_out transfer_in registers, when used as a source in an instruction, supply operands to the execution datapath. the specific register selected is either en coded in the instruction, or selected indirectly via indexing. transfer_in registers are written by external units based on the me requesting data from a resource outside of itself. transfer_out registers, when used as a destination in an instruction, are written with the result from the execution datapath. the specific register select ed is encoded in the instruction, or selected indirectly via indexing. these registers in turn supp ly data to external units when selected by that unit. 2.3.4 next neighbor registers next neighbor registers, when used as a source in an instruction, supply operands to the execution datapath. they are written either by the adjacent me or by the same me they are in. when next neighbor is used as a destination in an instruction; the instruction result data is sent out of the me to the adjacent me. 2.3.5 local memory (lm) local memory is addressable storage located in the me. lm is read and written exclusively under program control. lm supplies operands to the execution datapath as a source, and receives results as a destination. the specific lm location selected is based on the value in one of the lm_addr registers which are written by local_csr_wr instructions. there are two lm_addr registers per
intel ? IXP2400 network processor 16 datasheet context and a working copy of each. when a context goes to sleep state, the value of the working copies is put into the context?s copy of lm_addr. when the context returns to the executing state, the value in its copy of lm_addr are put into the working copies. the choice of lm_addr_0 or lm_addr_1 is selected in the instruction. 2.3.6 crc unit the crc unit operates in parallel with the execution datapath. it takes two operands, performs a crc operation, and writes back a result. crc-16 and crc-32 are supported. one of the operands is the crc_remainder local csr, and the other is a gpr, transfer in register, next neighbor, or lm, specified in the instruction and passed through the execution datapath to the crc unit. the instruction specifies the crc operation type. 2.3.7 event signals event signals are used to coordinate a program with completion of external events. for example, when a me issues a command to an external unit to read data (which will be written into a transfer_in register), the program must ensure that it does not try to use the data until the external unit has written it. there is no hardware mechanism to flag that a register write is pending, and then prevent the program from using it. instead the coordination is under software control, with hardware support. when the program issues the command to the extern al event, it can reques t that the external unit supply an indication (called an event signal) that the command ha s been completed. there are 15 event signals per context that can be used, an d local csrs per context to track which event signals are pending and which have been returned. the event signals can be used to move a context from sleep state to ready state, or altern atively, the program can test and branch on the status of event signals. event signals can be set in nine different ways: 1. when data is written into s_transfer_in registers (part of s_push_id input) 2. when data is written into d_transfer_in registers (part of d_push_id input) 3. when data is taken from s_transfer_out registers (part of s_pull_id input) 4. when data is taken from d_transfer_out registers (part of d_pull_id input) 5. on interthread_sig_in input 6. on nn_sig_in input 7. on prev_sig_in input 8. on write to same_me_signal local csr 9. by internal timer 2.4 ddr sdram the ddr memory controller controls the off-chip dram. the ddr controller contains the mechanism that allows the other functional units to access the single channel of dram present in the IXP2400. dram sizes of 64 mb, 128 mb, 512 mb and 1 gb are supported. single-sided or double-sided dimms are supported. the IXP2400 only supports 4-bank ddr devices. table 1 shows the supported configurations. the addressing capability of the ddr controller is 2 gb. the address space always appears contiguous to software executing on the IXP2400. if less than 2 gb
intel ? IXP2400 network processor datasheet 17 of physical memory is present, the upper part of the address space is not utilized. read and writes to dram generated by the mes, the intel xscale co re, and pci units, are presented as requests to the ddr controller, which enqueues them to their respective bank(s). error correction code (ecc) is supported. each 64 bits (8 bytes) has an 8-bit ecc associated with it, thus all single bit errors are corrected while multiple bit errors are detected and optionally reported. the ecc operation can be disabled. when ecc is enabled, partial writes (writes of less than 8 bytes) will be performed as read-modify-write by the ddr controller. 2.5 sram the IXP2400 has two independent sram controllers, each of which supports pipelined qdr synchronous static ram (sram) and/or a coprocessor that adheres to qdr signaling. either controller can be left unused if the application do es not need to use its sram channels, which are accessible by the microengines, the intel xscale core, and the pci unit (external bus masters). the memory is logically four bytes (32 bits) wide; physically the data pins are two bytes wide and are double clocked. byte parity is supported. each of the four bytes has a parity bit, which is generated when the byte is written and checked when the data is read. there are byte enables that select which bytes to write for writes of less than 32 bits. examples of supported srams are: table 1. ddr supported configurations memory capacity dram density part width total number of sdrams number of dimms number of sides comments (sample dimm vendors shown) 64 mb 64 mbit x8 9 1 1 128 mbit x16 5 1 1 128 mb 64 mbit x8 18 1 2 128 mbit x8 9 1 1 samsung*, micron* 128 mbit x16 10 1 2 256 mbit x16 5 1 1 256 mb 128 mbit x8 18 1 2 samsung*, micron* 256 mbit x16 10 1 2 samsung* 256 mbit x16 10 1 2 512 mbit x16 5 1 1 512 mb 256 mbit x8 18 1 2 samsung*, micron* 512 mbit x8 9 1 1 512 mbit x16 10 1 2 1.0 gbit x16 5 1 1 1.0 gb 512 mbit x 8 18 1 2 1.0 gbit x 8 9 1 1 1.0 gbit x16 10 1 2 2.0 gb 1.0 gbit x8 18 1 2
intel ? IXP2400 network processor 18 datasheet samsung* 36-mb qdrii x9 k7r320982m-fc20 or 36-mb qdrii x18 k7r321882m-fc20 sram idt* idt71t6280h 9-mb pipelined qdr sram burst of 2 (512k x 18) cypress* cy7c1302v25 9-mb pipelined sram with qdr architecture (512k x 18) each of the two qdr ports are qdr- and qdrii-c ompatible. each port implements the ?_k? and ?_c? output clocks as an input and their inversions . the ?_c? clocks are used for reading sram data and the ?_k? clocks are used for writing sram data. extensive work has been performed to control the impedance within the IXP2400 for IXP2400-initiated signals that drive qdr parts. the receivers of IXP2400 qdr have on-die termination. the IXP2400 io driver/receiver can drive up to four qdr device loads. the IXP2400 supports bursts of two sram devices. the IXP2400 uses one pair of the cn/cn# clocks for read data; the other pair is terminated on the die. the sram controller can also be configured to in terface to an external coprocessor that adheres to the qdr electricals and protocol. 2.5.1 sram controller configurations each channel has enough address pins (24) to support up to 64 mb of sram. the sram controllers can directly generate multiple port enables (up to four pairs) to allow for depth expansion. two pairs of pins are dedicated for port enables. smaller rams use fewer address figure 7. clock configuration b0059-01 clam-shelled srams c/c# c/c# package balls package balls termination intel? IXP2400 network processor c1n/c1n# k1/k1# k/k# k/k# c/c# c/c# c1/c1# k2/k2# c2/c2# c1/c1# c2/c2# c2n/c2n# termination vtt 50 ? 50 ? note: leave cq/cq# as nc. vtt
intel ? IXP2400 network processor datasheet 19 signals than the number provided to accommodate the largest rams, so some address pins (23:20) are configurable as either address- or port-enable based on csr setting as shown in table 2 . note that all of the srams on a given channel must be the same size. each channel can be expanded by depth according to the number of port enables available. if external decoding is used, then the number of srams used is not limited by the number of port enables generated by the sram controller. note: external decoding may require external pipeline registers to account for the decode time, depending on the desired frequency. maximum sram system sizes are shown in table 3 . shaded entries require external decoding, because they use more port enables than the sram controller can supply directly. 2.6 media and switch fabric interface 2.6.1 phy modes supported the media and switch fabric (msf) interface co nnects the IXP2400 to a physical layer device (phy) and/or a switch fabric interface. msf consists of the following external interfaces: receive and transmit interfaces, each of which can be individually configured for either utopia (level 1, 2, and 3), pos-phy (level 2 and 3) or csix protocols. table 2. sram controller configurations sram configuration sram size addresses needed to index sram addresses used as port enables total number of port select pairs available 512k x 18 1 mb 17:0 23:22, 21:20 4 1m x 18 2 mb 18:0 23:22, 21:20 4 2m x 18 4 mb 19:0 23:22, 21:20 4 4m x 18 8 mb 20:0 23:22 3 8m x 18 16 mb 21:0 23:22 3 16m x 18 32 mb 22:0 none 2 32m x 18 64 mb 23:0 none 1 table 3. total memory per channel sram size number of srams on channel 12345678 512k x 18 1 mb 2 mb 3 mb 4 mb 5 mb 6 mb 7 mb 8 mb 1m x 18 2 mb 4 mb 6 mb 8 mb 10 mb 12 mb 14 mb 16 mb 2m x 18 4 mb 8 mb 12 mb 16 mb 20 mb 24 mb 28 mb 32 mb 4m x 18 8 mb 16 mb 24 mb 32 mb 64 mb na na na 8m x 18 16 mb 32 mb 48 mb 64 mb na na na na 16m x 18 32 mb 64 mb na na na na na na 32m x 18 64 mb na na na na na na na
intel ? IXP2400 network processor 20 datasheet a flow control interface, which provides a poin t-to-point connection used to pass csix-l1-b flow control c-frames either between two IXP2400 network processors or between a IXP2400 and a csix-l1-b switch fabric. each 32-bit interface can be subdivided into 8- or 16-bit channel combinations. the msf interface uses 3.3v lvttl (low-voltage transistor-transistor logic) signaling. while the csix standard is a source-synchronous bus, the IXP2400 uses a common-clocking scheme for compatibility with the other protocols. in utopia and pos-phy modes, each port can function as a single 32-bit interface, or can be subdivided into a combination of 8- or 16-bit ch annels. each channel is a point-to-point connection to a single physical layer device. each channe l operates independently when subdivided. in addition to single-phy mode, the IXP2400 supports multi-phy (mphy) mode. in mphy mode, the 32-bit bus is shared by up to 16 ports in accordance with the utopia level 3 and pos phy level 3 specifications. master mode only is supported in utopia and pos-phy modes. note: spi3 is the name associated with pos-phy level 3. the optical inter-networking forum (oif) co ntrols the spi3 implem entation agreement document (available at http://www.oiforum.com). 2.6.2 csix the IXP2400 implements csix_l1 (common switch interface) for signalling and clocks. csix_l1 defines an interface between a traffic manager (tm) and a switch fabric (sf) for atm, ip, mpls, ethernet, and similar data communicati ons applications. the basic unit of information transferred between tms and sfs is called a cframe. there are a number of cframe types defined, but they can be basically categori zed as either data, control, or flow control. associated with each cframe is information such as length, type, ad dress. this information is collected by the msf and passed to microengines. the network processor forum (npf) controls the csix_l1 specification (available at http://www.npforum.org). 2.7 pci controller the pci controller provides 64-bit, 66-mhz-capable pci rev. 2.2 in terface. it is also compatible to 32-bit and/or 33-mhz pci devices. the pci controller provides the following functions: target access (external bus master access to sram, dram, and csrs) master access (intel xscale core or microengine access to pci target devices) three dma channels mailbox and doorbell registers for in tel xscale core-to-host communication pci arbiter the IXP2400 can be configured to act as pci central function, or can own the arbitration.
intel ? IXP2400 network processor datasheet 21 2.8 xpi unit 2.8.1 gpio the IXP2400 contains eight general-purpose io (g pio) pins. these can be programmed as either input or output, and can be used for slow-speed io , such as leds or input switches. they can also be used as interrupts to the intel xscale core, or to clock the programmable timers. 2.8.2 serial port the IXP2400 contains a standard rs-232?compatible universal asynchronous receiver/transmitter (uart), which can be used for communication with a debugger or maintenance console. modem controls are not supported; if they are need ed, gpio pins can be used for that purpose. the uart performs serial-to-parallel conversion on data characters received from a peripheral device and parallel-to-serial conversion on data characters received from the processor. the processor can read the complete status of the uart at any time during operation. available status information includes the type and condition of the transfer operations being performed by the uart and any error conditions (parity, overrun, framing or break interrupt). the serial ports can operate in either fifo or non-fifo mode. in fifo mode, a 64-byte transmit fifo holds data from the processor to be transmi tted on the serial link and a 64-byte receive fifo buffers data from the serial link until read by the processor. the uart includes a programmable baud rate genera tor that is capable of dividing the internal clock input (apb_clk, running at 50 mhz) by divisors of 1 to 2 16 - 1, and produces a 16x clock to drive the internal transmitter logic. it also drives the receive logic. the uart can be operated in polled or in interrupt-driven mode as selected by software. the uart has two clocks: the clock from the baud rate generator for transmit and receive operation, and the clock from the xpi unit for register reads and writes. 2.8.3 slowport the slowport is an external interface to the ix p2400 and is used for flash memory access and 8-, 16-, or 32-bit asynchronous device access. it allows the intel xscale core to do read/ write data transfers to these slave devices. the address bus and data bus are multiplexed to reduce the pin count. in addition, the address bus is also compressed from a[24:0] down to a[7:0] and shifted out with three clock cycles in mode 0, and four clock cycles in mode 1?4. therefore, an external set of buffers is needed to latch the address. two chip selects are provided. several mo des of configurations are supported to connect with the microprocessor control port of various framers or mac devices. see figure 8 for an example configuration (note that the ack signal is optional).
intel ? IXP2400 network processor 22 datasheet figure 8. example slowport connection a9861-01 sp_rd_l sp_cs_l[0] sp_cs_l[1] sp_a[1:0] ce# cp d[7:0] q[7:0] 74f377 sp_wr_l oe_l a[1:0] cs_l we_l d[7:0] a[24:2] a[1:0] cs_l we_l d[7:0] ack_l a[24:2] intel ? IXP2400 and intel ? ixp2800 network processors sp_ad[7:0] sp_ale_l sp_clk sp_ack_l ce# cp d[7:0] a[24:18] a[17:10] a[9:2] q[7:0] 74f377 ce# cp d[7:0] q[7:0] 74f377 oe_l
intel ? IXP2400 network processor datasheet 23 3.0 signal description 3.1 ballout functional groupings diagram figure 9 provides a high-level overview of the general groupings of the balls by function. note that the following ball locations are unpopulated: a1, y1, w1, v1, y37, w37, v37, au[18:20], and a[18:20]. 3.2 ball descriptions grouped by function this section gives an overview of the IXP2400 io signals. detailed definitions and description of the use of signals can be found in chapters of the specification specific to each interface. figure 9. high-level overview of ballout functional groupings diagram (ball side) a9843-01 unpopulated y1, w1, v1 unpopulated au[18:20] unpopulated a[18:20] unpopulated a1 unpopulated y37, w37, v37 ddr sram gpio / misc pci msf vcc / vss
intel ? IXP2400 network processor 24 datasheet IXP2400 signals are categorized into one of several groups: dram, sram, media and switch fabric interface, pci, gpio, slowport (serial rom), serial port, clocks, and jtag and test. 3.2.1 ddr sdram there is one double-data-rate (ddr) dram channel, having the signals found in table 4 . the ddr sdram interface is clocked at 100 or 150 mhz with data transfers on both edges of the clock. the sdrams use sstl_2 signaling levels per the jedec jesd79 specification. 3.2.2 sram there are two sram interfaces to quad-data-rate (qdr) srams. each interface has the signals found in table 5 . the srams use hstl signaling levels. qdr sram datasheets typically document the data and parity signals as d[17:0]. the IXP2400 signal documentation splits up the data and parity signals, in terms of data[7:0], data[15:8], parity[0], and parity[1]. the data[7:0] signals should be connected to qdr sram d[7:0]. the data[15:8] signals should be connected to qdr sram d[16:9]. the parity[0] signal should be connected to qdr sram d[8]. the parity[1] signal should be connected to qdr sram d[17]. table 4. ddr sdram signals signal name i/o description number d_ck[2:0] o positive master clock 3 d_ck_l[2:0] o negative master clock 3 d_cs_l[1:0] o chip selects 2 d_ras_l o row address strobe 1 d_cas_l o column address strobe 1 d_we_l o write enable 1 d_dm[8:0] o data mask (write data) 9 d_ba[1:0] o bank address selects 2 d_a[13:0] o address 14 d_dq[63:0] i/o data 64 d_ecc[7:0] i/o error correction code bits 8 d_dqs[8:0] i/o data strobes 9 d_rcvenout_l o output clock for source synchronous reads 1 d_rcvenin_l i input clock for source synchronous reads 1 d_rcomp[1:0] i buffer compensation 1 1. the IXP2400 uses a compensation signal to adjust the system memory buffer characteristics over temperature, process, and voltage variations. the ddr pins d_rcomp[1] and d_rcomp[0] should be connected to the ddr termination voltage (1.25v) through a 30 ? 1% resistor and one 0603 0.1 f decoupling capacitor to ground. place the resistor and capacitor as close to the IXP2400 as possible, within 1.0? of the package. the compensation signal and the vtt trace should be routed with as wide a trace as possible, minimum of 12 mils wide and isolated from other signals with a minimum of 10-mil spacing. 2 d_vref[1:0] i voltage reference 2 d_cke[1:0] o clock enables used by controller during initialization 2 total (per channel) 125
intel ? IXP2400 network processor datasheet 25 3.2.3 media and switch fabric (msf) interface in table 6 , the use of the pins is based on whether or not the port is in utopia, pos-phy, or csix mode. table 6 shows how the external pin names map to the signal names referenced in the utopia, pos-phy, and csix specifications. the table shows all the possible signals that could be used for a particular standard. however, a particular mode within a standard, such as mphy or sphy, will not necessarily use all the signals shown in a column. note: the media bus is 3.3v lvttl using globally synchronous (common) clocking. thus the bus does not have electrical or clocking compatibility with the csix-l1 specification, which is 2.5v lvcmos with source synchronous clocking. each interface has two clocks; rxclk01/txclk01 is used by the ports associated with bits [15:0]; rxclk23/txclk23 is used by the ports associated with bits[31:16]. this applies only to the 4 x 8, 2 x 16, and 1 x 16 + 2 x 8 sphy modes, and allows each half of the bus to be clocked independently. in 1 x 32 sphy, mphy, or csix modes, only rxclk01/txclk01 is used and is internally routed to all the logic; rxclk23 and txclk23 are tied to ground. table 5. sram signals signal name i/o description number sn_k[1:0] o positive and negative output clocks. address, port enable, data out are referenced to these clocks. 2 sn_k_l[1:0] o 2 sn_c[1:0] o positive and negative output clocks used to generate sn_cin[1:0] and sn_cin_l[1:0] 2 sn_c_l[1:0] o 2 sn_cin[1:0] i positive and negative clock inputs. they are the feedback of sn_c[1:0] and sn_c_l[1:0]. 2 sn_cin_l[1:0] i 2 sn_di[15:0] i data input bus 16 sn_pi[1:0] i byte parity for data in; pi[1] for di[15:8], and pi[0] for di[7:0] 2 sn_do[15:0] o data output bus 16 sn_po[1:0] o byte parity for data out; po[1] for do[15:8], and po[0] for do[7:0] 2 sn_bwe_l[1:0] o byte write enables; asserted to enable writing each byte during writes. 2 sn_rpe_l[1:0] o read port enable; asserted to start a read. 2 sn_wpe_l[1:0] o write port enable; asserted to start a write. sn_a[23:0] o address to srams. some addresses signals can be programmed to act as additional port enables (via csr control). 24 sn_vref hstl reference voltage 1 sn_zq[1:0] i impedance match 1 1. qdr uses a similar compensation scheme as ddr. however, the voltage references are different. the pins s0_zq[0] and s1_zq[0] must each be separately connected to ground through a high precision 50 ? resistor and one 0603 0.1 f decou- pling capacitor. the pins s0_zq[1] and s1_zq[1] should each be separately connected to qdr io voltage (1.5v) thorough a high precision 50 ? resistor and one 0603 0.1 f decoupling capacitor. place the resistor and capacitor as close to the IXP2400 as possible, within 1.0? of the package. the compensation signal and the vtt trace should be routed with as wide a trace as possible, minimum of 12 mils wide and isolated from other signals with a minimum of 10-mil spacing. 2 total (per channel) 81
intel ? IXP2400 network processor 26 datasheet table 6. msf data signals pin name i/o type description number rxclk23 i lvttl receive clock for channel 2 and 3 1 rxclk01 i lvttl receive clock for channel 0 and 1 1 rxenb[3:0] o lvttl receive enable 4 rxsof[3:0] i lvttl receive start of frame 4 rxeof[3:0] i lvttl receive end of frame 4 rxval[3:0] i lvttl receive data valid 4 rxerr[3:0] i lvttl receive data error 4 rxprty[3:0] i lvttl receive data parity 4 rxfa[3:0] i lvttl received cell/frame available 4 rxaddr[3:0] o lvttl receive phy address 4 rxpfa i lvttl receive (polled) frame available 1 rxpadl[1:0] i lvttl these are the same signals as rmod[1:0] in spi3 and pos phy l2. 2 rxdata[31:0] i lvttl receive data 32 txclk23 i lvttl transmit clock for channel 2 and 3 1 txclk01 i lvttl transmit clock for channel 0 and 1 1 txenb[3:0] o lvttl transmit enable 4 txsof[3:0] o lvttl transmit start of frame 4 txeof[3:0] o lvttl transmit end of frame 4 txerr[3:0] o lvttl transmit error indicator 4 txprty[3:0] o lvttl transmit bus parity 4 txfa[3:0] i lvttl transmit cell buffer available 4 txaddr[3:0] o lvttl transmit address of phy 4 txpfa i lvttl transmit polled phy frame available 1 txsfa i lvttl transmit selected phy frame available 1 txpadl[1:0] o lvttl transmit modulo. they are the same signals as tmod[1:0] in spi3 and pos phy l2. 2 txdata[31:0] o lvttl transmit data 32 txrcomp 1 ilvttl transmitter compensation resistor 1
intel ? IXP2400 network processor datasheet 27 notes: 1. the msf txrcomp and rxrcomp pins should be separately connected to ground through external 45 ? 1% resistor and one 0603 0.1 f decoupling capacitor. place the resistor and capacitor as close to the IXP2400 as possible, within 1.0? of the package. t he compensation signal should be routed with as wide a trace as possible, minimum of 12 mils wide and isolated from other signals with a minimum of 10-mil spacing. 2. msf_clk_bypass is used for debug only. if the msf pll fails to work, asserting this signal enables the buffered external clock to bypass the pll to connect to the internal msf clock trees. in normal operation, it should be tied to low. see table 22 ?cbus pinout? on page 62 for information regarding signals used to communicate flow control information between two IXP2400 network processors. 3.2.3.1 msf mode signal usage the following tables specify the signal usag e for each mode supported by the msf and the mapping of these signals to the msf pinout. 1. table 7 , table 8 , table 9 , and table 10 describe the utopia and pos-phy sphy modes. in these modes, the bus is configured as 1x32, 2x16, 4x8, or 1x16+2x8, and the ports may be any combination of utopia or pos-phy sphy ports, master or slave. 2. table 11 describes x32 utopia level 3 mphy mode pinout. 3. table 12 describes x32 pos-phy level 3 mphy mode pinout. 4. table 13 describes csix/cbus mode pinout. 5. table 14 and table 15 describe x16 utopia level 2 mphy mode with one x16 or two x8 sphy ports. the sphy ports may be any combination of utopia or pos-phy, master or slave. 6. table 16 and table 17 describe x16 pos-phy level 2 mphy mode with one x16 or two x8 sphy ports. the sphy ports may be any combination of utopia or pos-phy, master or slave. 7. the pin names assume master mode operation. in slave mode operation, the pins have a different meaning. table 18 , table 19 , table 20 , and table 21 describe the master pin name to slave function mapping for various bus widths. 8. table 22 describes the cbus pinout. rxrcomp 1 ilvttl receiver compensation resistor 1 msf_clk_b ypass 2 ilvttl media switch fabric pll bypass 1 rsvd[3:0] reserved pins. these pins should be no connect. 4 total (per channel) 142 table 6. msf data signals (continued) pin name i/o type description number
intel ? IXP2400 network processor 28 datasheet table 7. 1x32 sphy utopia/pos-phy master mode port master pin name direction notes port 3 (unused) rxclk23 input unused; tie to ground rxenb[3] output unused; no connect rxsof[3] input unused; tie to ground rxeof[3] input unused; tie to ground rxval[3] input unused; tie to ground rxerr[3] input unused; tie to ground rxprty[3] input unused; tie to ground rxfa[3] input unused; tie to ground port 2 (unused) rxclk23 input unused; tie to ground rxenb[2] output unused; no connect rxsof[2] input unused; tie to ground rxeof[2] input unused; tie to ground rxval[2] input unused; tie to ground rxerr[2] input unused; tie to ground rxprty[2] input unused; tie to ground rxfa[2] input unused; tie to ground port 1 (unused) rxclk01 input rxenb[1] output unused; no connect rxsof[1] input unused; tie to ground rxeof[1] input unused; tie to ground rxval[1] input unused; tie to ground rxerr[1] input unused; tie to ground rxprty[1] input unused; tie to ground rxfa[1] input unused; tie to ground port 0 rxclk01 input rxenb[0] output rxsof[0] input rxeof[0] input not used in utopia mode, tie to ground rxval[0] input not used in utopia mode, tie to ground rxerr[0] input not used in utopia mode, tie to ground rxprty[0] input rxfa[0] input not used in pos-phy level 3 sphy mode, tie to ground rxdata[31:0] input rxpadl[1:0] input not used in utopia mode, tie to ground mphy (unused) rxaddr[3:0] output unused; no connect rxpfa input unused; tie to ground
intel ? IXP2400 network processor datasheet 29 port 3 (unused) txclk23 input unused; tie to ground txenb[3] output unused; no connect txsof[3] output unused; no connect txeof[3] output unused; no connect txerr[3] output unused; no connect txprty[3] output unused; no connect txfa[3] input unused; tie to ground port 2 (unused) txclk23 input unused; tie to ground txenb[2] output unused; no connect txsof[2] output unused; no connect txeof[2] output unused; no connect txerr[2] output unused; no connect txprty[2] output unused; no connect txfa[2] input unused; tie to ground port 1 (unused) txclk01 input txenb[1] output unused; no connect txsof[1] output unused; no connect txeof[1] output unused; no connect txerr[1] output unused; no connect txprty[1] output unused; no connect txfa[1] input unused; tie to ground port 0 txclk01 input txenb[0] output txsof[0] output txeof[0] output not used in utopia mode, no connect txerr[0] output not used in utopia mode, no connect txprty[0] output txfa[0] input txpadl[1:0] output not used in utopia mode, no connect txdata[31:0] output mphy (unused) txpfa input unused; tie to ground txsfa input unused; tie to ground txaddr[3:0] output unused; no connect table 7. 1x32 sphy utopia/pos-phy master mode (continued) port master pin name direction notes
intel ? IXP2400 network processor 30 datasheet table 8. 2x16 sphy utopia/pos master mode port master pin name direction notes port 3 (unused) rxclk23 input rxenb[3] output unused; no connect rxsof[3] input unused; tie to ground rxeof[3] input unused; tie to ground rxval[3] input unused; tie to ground rxerr[3] input unused; tie to ground rxprty[3] input unused; tie to ground rxfa[3] input unused; tie to ground port 2 rxclk23 input rxenb[2] output rxsof[2] input rxeof[2] input not used in utopia mode, tie to ground rxval[2] input not used in utopia mode, tie to ground rxerr[2] input not used in utopia mode, tie to ground rxprty[2] input rxfa[2] input not used in pos-phy level 3 sphy mode, tie to ground rxpadl[1] input not used in utopia mode, tie to ground rxdata[31:16] input port 1 rxclk01 input rxenb[1] output unused; no connect rxsof[1] input unused; tie to ground rxeof[1] input unused; tie to ground rxval[1] input unused; tie to ground rxerr[1] input unused; tie to ground rxprty[1] input unused; tie to ground rxfa[1] input unused; tie to ground port 0 rxclk01 input rxenb[0] output rxsof[0] input rxeof[0] input not used in utopia mode, tie to ground rxval[0] input not used in utopia mode, tie to ground rxerr[0] input not used in utopia mode, tie to ground rxprty[0] input rxfa[0] input not used in pos-phy level 3 sphy mode, tie to ground rxpadl[0] input not used in utopia mode, tie to ground rxdata[15:0] input
intel ? IXP2400 network processor datasheet 31 mphy (unused) rxaddr[3:0] output unused; no connect rxpfa input unused; tie to ground port 3 (unused) txclk23 input txenb[3] output unused; no connect txsof[3] output unused; no connect txeof[3] output unused; no connect txerr[3] output unused; no connect txprty[3] output unused; no connect txfa[3] input unused; tie to ground port 2 txclk23 input txenb[2] output txsof[2] output txeof[2] output not used in utopia mode, no connect txerr[2] output not used in utopia mode, no connect txprty[2] output txfa[2] input txpadl[1] output not used in utopia mode, no connect txdata[31:16] output port 1 (unused) txclk01 input txenb[1] output unused; no connect txsof[1] output unused; no connect txeof[1] output unused; no connect txerr[1] output unused; no connect txprty[1] output unused; no connect txfa[1] input unused; tie to ground port 0 txclk01 input txenb[0] output txsof[0] output txeof[0] output not used in utopia mode, no connect txerr[0] output not used in utopia mode, no connect txprty[0] output txfa[0] input txpadl[0] output not used in utopia mode, no connect txdata[15:0] output mphy (unused) txpfa input unused; tie to ground txsfa input unused; tie to ground txaddr[3:0] output unused; no connect table 8. 2x16 sphy utopia/pos master mode (continued) port master pin name direction notes
intel ? IXP2400 network processor 32 datasheet table 9. 4x8 sphy utopia/pos-phy master mode port master pin name direction slave mode function and description port 3 rxclk23 input rxenb[3] output rxsof[3] input rxeof[3] input not used in utopia mode, tie to ground rxval[3] input not used in utopia mode, tie to ground rxerr[3] input not used in utopia mode, tie to ground rxprty[3] input rxfa[3] input not used in pos-phy level 3 sphy mode, tie to ground rxdata[31:24] input port 2 rxclk23 input rxenb[2] output rxsof[2] input rxeof[2] input not used in utopia mode, tie to ground rxval[2] input not used in utopia mode, tie to ground rxerr[2] input not used in utopia mode, tie to ground rxprty[2] input rxfa[2] input not used in pos-phy level 3 sphy mode, tie to ground rxpadl[1] input not used in utopia mode, tie to ground; not used in pos-phy x8 mode, tie to ground rxdata[23:16] input port 1 rxclk01 input rxenb[1] output rxsof[1] input rxeof[1] input not used in utopia mode, tie to ground rxval[1] input not used in utopia mode, tie to ground rxerr[1] input not used in utopia mode, tie to ground rxprty[1] input rxfa[1] input not used in pos-phy level 3 sphy mode, tie to ground rxdata[15:8] input
intel ? IXP2400 network processor datasheet 33 port 0 rxclk01 input rxenb[0] output rxsof[0] input rxeof[0] input not used in utopia mode, tie to ground rxval[0] input not used in utopia mode, tie to ground rxerr[0] input not used in utopia mode, tie to ground rxprty[0] input rxfa[0] input not used in pos-phy level 3 sphy mode, tie to ground rxpadl[0] input not used in utopia mode, tie to ground; not used in pos-phy x8 mode, tie to ground rxdata[7:0] input mphy (unused) rxaddr[3:0] output unused; no connect rxpfa input unused; tie to ground port 3 txclk23 input txenb[3] output txsof[3] output txeof[3] output not used in utopia mode, no connect txerr[3] output not used in utopia mode, no connect txprty[3] output txfa[3] input txdata[31:24] output port 2 txclk23 input txenb[2] output txsof[2] output txeof[2] output not used in utopia mode, no connect txerr[2] output not used in utopia mode, no connect txprty[2] output txfa[2] input txpadl[0] output not used in utopia mode, no connect; not used in pos-phy x8 mode, no connect txdata[23:16] output table 9. 4x8 sphy utopia/pos-phy master mode (continued) port master pin name direction slave mode function and description
intel ? IXP2400 network processor 34 datasheet port 1 txclk01 input txenb[1] output txsof[1] output txeof[1] output not used in utopia mode, no connect txerr[1] output not used in utopia mode, no connect txprty[1] output txfa[1] input txdata[15:8] output port 0 txclk01 input txenb[0] output txsof[0] output txeof[0] output not used in utopia mode, no connect txerr[0] output not used in utopia mode, no connect txprty[0] output txfa[0] input txpadl[0] output not used in utopia mode, no connect; not used in pos-phy x8 mode, no connect txdata[7:0] output mphy (unused) txpfa input unused; tie to ground txsfa input unused; tie to ground txaddr[3:0] output unused; no connect table 10. 1x16+2x8 sphy utopia/pos master mode port master pin name direction slave mode function and description port 3 rxclk23 input rxenb[3] output rxsof[3] input rxeof[3] input not used in utopia mode, tie to ground rxval[3] input not used in utopia mode, tie to ground rxerr[3] input not used in utopia mode, tie to ground rxprty[3] input rxfa[3] input not used in pos-phy level 3 sphy mode, tie to ground rxdata[31:24] input table 9. 4x8 sphy utopia/pos-phy master mode (continued) port master pin name direction slave mode function and description
intel ? IXP2400 network processor datasheet 35 port 2 rxclk23 input rxenb[2] output rxsof[2] input rxeof[2] input not used in utopia mode, tie to ground rxval[2] input not used in utopia mode, tie to ground rxerr[2] input not used in utopia mode, tie to ground rxprty[2] input rxfa[2] input not used in pos-phy level 3 sphy mode, tie to ground rxpadl[1] input not used in utopia mode, tie to ground; not used in pos-phy x8 mode, tie to ground rxdata[23:16] input port 1 (unused) rxclk01 input rxenb[1] output unused; no connect rxsof[1] input unused; tie to ground rxeof[1] input unused; tie to ground rxval[1] input unused; tie to ground rxerr[1] input unused; tie to ground rxprty[1] input unused; tie to ground rxfa[1] input unused; tie to ground port 0 rxclk01 input rxenb[0] output rxsof[0] input rxeof[0] input not used in utopia mode, tie to ground rxval[0] input not used in utopia mode, tie to ground rxerr[0] input not used in utopia mode, tie to ground rxprty[0] input rxfa[0] input not used in pos-phy level 3 sphy mode, tie to ground rxpadl[0] input not used in utopia mode, tie to ground rxdata[15:0] input mphy (unused) rxaddr[3:0] output unused; no connect rxpfa input unused; tie to ground table 10. 1x16+2x8 sphy utopia/pos master mode (continued) port master pin name direction slave mode function and description
intel ? IXP2400 network processor 36 datasheet port 3 txclk23 input txenb[3] output txsof[3] output txeof[3] output not used in utopia mode, no connect txerr[3] output not used in utopia mode, no connect txprty[3] output txfa[3] input txdata[31:24] output port 2 txclk23 input txenb[2] output txsof[2] output txeof[2] output not used in utopia mode, no connect txerr[2] output not used in utopia mode, no connect txprty[2] output txfa[2] input txpadl[1] output not used in utopia mode, no connect; not used in pos-phy x8 mode, no connect txdata[23:16] output port 1 (unused) txclk01 input txenb[1] output txsof[1] output txeof[1] output not used in utopia mode, no connect txerr[1] output not used in utopia mode, no connect txprty[1] output txfa[1] input port 0 txclk01 input txenb[0] output txsof[0] output txeof[0] output not used in utopia mode, no connect txerr[0] output not used in utopia mode, no connect txprty[0] output txfa[0] input txpadl[0] output not used in utopia mode, no connect txdata[15:0] output mphy (unused) txpfa input unused; tie to ground txsfa input unused; tie to ground txaddr[3:0] output unused; no connect table 10. 1x16+2x8 sphy utopia/pos master mode (continued) port master pin name direction slave mode function and description
intel ? IXP2400 network processor datasheet 37 table 11. x32 utopia level 3 mphy mode port master pin name direction notes port 3 (unused) rxclk23 input unused; tie to ground rxenb[3] output unused; no connect rxsof[3] input unused; tie to ground rxeof[3] input unused; tie to ground rxval[3] input unused; tie to ground rxerr[3] input unused; tie to ground rxprty[3] input unused; tie to ground rxfa[3] input used only in mphy-4 direct status mode port 2 (unused) rxclk23 input unused; tie to ground rxenb[2] output unused; no connect rxsof[2] input unused; tie to ground rxeof[2] input unused; tie to ground rxval[2] input unused; tie to ground rxerr[2] input unused; tie to ground rxprty[2] input unused; tie to ground rxfa[2] input used only in mphy-4 direct status mode port 1 (unused) rxclk01 input rxenb[1] output unused; no connect rxsof[1] input unused; tie to ground rxeof[1] input unused; tie to ground rxval[1] input unused; tie to ground rxerr[1] input unused; tie to ground rxprty[1] input unused; tie to ground rxfa[1] input used only in mphy-4 direct status mode
intel ? IXP2400 network processor 38 datasheet port 0 (mphy) rxclk01 input rxenb[0] output rxsof[0] input rxeof[0] input unused; tie to ground rxval[0] input unused; tie to ground rxerr[0] input unused; tie to ground rxprty[0] input rxfa[0] input used only in mphy-4 direct status mode rxdata[31:0] input rxpadl[1:0] input unused; tie to ground txcsrb output rxaddr[4] rxaddr[3:0] output rxpfa input used only in mphy-4/mphy-32 polled status mode port 3 (unused) txclk23 input unused; tie to ground txenb[3] output unused; no connect txsof[3] output unused; no connect txeof[3] output unused; no connect txerr[3] output unused; no connect txprty[3] output unused; no connect txfa[3] input used only in mphy-4 direct status mode port 2 (unused) txclk23 input unused; tie to ground txenb[2] output unused; no connect txsof[2] output unused; no connect txeof[2] output unused; no connect txerr[2] output unused; no connect txprty[2] output unused; no connect txfa[2] input used only in mphy-4 direct status mode port 1 (unused) txclk01 input txenb[1] output unused; no connect txsof[1] output unused; no connect txeof[1] output unused; no connect txerr[1] output unused; no connect txprty[1] output unused; no connect txfa[1] input used only in mphy-4 direct status mode table 11. x32 utopia level 3 mphy mode (continued) port master pin name direction notes
intel ? IXP2400 network processor datasheet 39 port 0 (mphy) txclk01 input txenb[0] output txsof[0] output txeof[0] output unused in utopia mode, no connect txerr[0] output unused in utopia mode, no connect txprty[0] output txfa[0] input used only in mphy-4 direct status mode txpadl[1:0] output unused in utopia mode, no connect txdata[31:0] output txpfa input used only in mphy-4/mphy-32 polled status mode txsfa input unused in utopia mode, tie to ground txenb[1] output txaddr[4] txaddr[3:0] output table 12. x32 pos-phy level 3 mphy mode port master pin name direction notes port 3 (unused) rxclk23 input unused; tie to ground rxenb[3] output unused; no connect rxsof[3] input unused; tie to ground rxeof[3] input unused; tie to ground rxval[3] input unused; tie to ground rxerr[3] input unused; tie to ground rxprty[3] input unused; tie to ground rxfa[3] input unused; tie to ground port 2 (unused) rxclk23 input unused; tie to ground rxenb[2] output unused; no connect rxsof[2] input unused; tie to ground rxeof[2] input unused; tie to ground rxval[2] input unused; tie to ground rxerr[2] input unused; tie to ground rxprty[2] input unused; tie to ground rxfa[2] input unused; tie to ground table 11. x32 utopia level 3 mphy mode (continued) port master pin name direction notes
intel ? IXP2400 network processor 40 datasheet port 1 (unused) rxclk01 input rxenb[1] output unused; no connect rxsof[1] input unused; tie to ground rxeof[1] input unused; tie to ground rxval[1] input unused; tie to ground rxerr[1] input unused; tie to ground rxprty[1] input unused; tie to ground rxfa[1] input unused; tie to ground port 0 (mphy) rxclk01 input rxenb[0] output rxsof[0] input rxeof[0] input rxval[0] input rxerr[0] input rxprty[0] input rxfa[0] input unused; tie to ground rxdata[31:0] input rxpadl[1:0] input txcsrb output unused; no connect rxaddr[3:0] output unused; no connect rxpfa input port 3 (unused) txclk23 input unused; tie to ground txenb[3] output unused; no connect txsof[3] output unused; no connect txeof[3] output unused; no connect txerr[3] output unused; no connect txprty[3] output unused; no connect txfa[3] input used only in mphy-4 direct status mode port 2 (unused) txclk23 input unused; tie to ground txenb[2] output unused; no connect txsof[2] output unused; no connect txeof[2] output unused; no connect txerr[2] output unused; no connect txprty[2] output unused; no connect txfa[2] input used only in mphy-4 direct status mode table 12. x32 pos-phy level 3 mphy mode (continued) port master pin name direction notes
intel ? IXP2400 network processor datasheet 41 port 1 (unused) txclk01 input txenb[1] output unused; no connect txsof[1] output unused; no connect txeof[1] output unused; no connect txerr[1] output unused; no connect txprty[1] output unused; no connect txfa[1] input used only in mphy-4 direct status mode port 0 (mphy) txclk01 input txenb[0] output txsof[0] output txeof[0] output txerr[0] output txprty[0] output txfa[0] input used only in mphy-4 direct status mode txpadl[1:0] output txdata[31:0] output txpfa input used only in mphy-4/mphy-32 polled status mode txsfa input unused, tie to ground txenb[1] output txaddr[4] txaddr[3:0] output table 13. 1x32 csix mode port master pin name direction notes port 3 (unused) rxclk23 input unused; tie to ground rxenb[3] output unused; no connect rxsof[3] input unused; tie to ground rxeof[3] input unused; tie to ground rxval[3] input unused; tie to ground rxerr[3] input unused; tie to ground rxprty[3] input unused; tie to ground rxfa[3] input unused; tie to ground table 12. x32 pos-phy level 3 mphy mode (continued) port master pin name direction notes
intel ? IXP2400 network processor 42 datasheet port 2 (unused) rxclk23 input unused; tie to ground rxenb[2] output unused; no connect rxsof[2] input unused; tie to ground rxeof[2] input unused; tie to ground rxval[2] input unused; tie to ground rxerr[2] input unused; tie to ground rxprty[2] input unused; tie to ground rxfa[2] input unused; tie to ground port 1 (unused) rxclk01 input rxenb[1] output unused; no connect rxsof[1] input unused; tie to ground rxeof[1] input unused; tie to ground rxval[1] input unused; tie to ground rxerr[1] input unused; tie to ground rxprty[1] input unused; tie to ground rxfa[1] input unused; tie to ground port 0 (csix rx) rxclk01 input rxenb[0] output unused; no connect rxsof[0] input rxeof[0] input unused; tie to ground rxval[0] input unused; tie to ground rxerr[0] input unused; tie to ground rxprty[0] input rxfa[0] input unused; tie to ground rxdata[31:0] input rxpadl[1:0] input unused; tie to ground rxaddr[3:0] output txcdat[7:4]; used only in x8 cbus mode rxpfa input unused; tie to ground cbus tx rxclk01 input txcsof output txcdat[3:0] output txcpar output txcsrb output txcfc output table 13. 1x32 csix mode (continued) port master pin name direction notes
intel ? IXP2400 network processor datasheet 43 port 3 (unused) txclk23 input unused; tie to ground txenb[3] output unused; no connect txsof[3] output unused; no connect txeof[3] output unused; no connect txerr[3] output unused; no connect txprty[3] output unused; no connect txfa[3] input unused; tie to ground port 2 (unused) txclk23 input unused; tie to ground txenb[2] output unused; no connect txsof[2] output unused; no connect txeof[2] output unused; no connect txerr[2] output unused; no connect txprty[2] output unused; no connect txfa[2] input unused; tie to ground port 1 (unused) txclk01 input txenb[1] output unused; no connect txsof[1] output unused; no connect txeof[1] output unused; no connect txerr[1] output unused; no connect txprty[1] output unused; no connect txfa[1] input rxcdat[7]; used only in x8 cbus mode port 0 (csix tx) txclk01 input rxcdat[6]; used only in x8 cbus mode txenb[0] output unused; no connect txsof[0] output txeof[0] output unused; no connect txerr[0] output unused; no connect txprty[0] output txfa[0] input unused; tie to ground txpadl[1:0] output unused; no connect txdata[31:0] output txpfa input rxcdat[5]; used only in x8 cbus mode txsfa input rxcdat[4]; used only in x8 cbus mode txaddr[3:0] output unused; no connect table 13. 1x32 csix mode (continued) port master pin name direction notes
intel ? IXP2400 network processor 44 datasheet cbus rx rxcsof input rxcdat[3:0] input rxcpar input rxcsrb input rxcfc output table 14. x16 utopia level 2 mphy-32 + x16 sphy (utopia or pos-phy) mode port pin name direction master mode function and description slave mode function and description port 3 (unused) rxclk23 input rxclk23 txclk23 rxenb[3] output unused; no connect unused, no connect rxsof[3] input unused; tie to ground unused; tie to ground rxeof[3] input unused; tie to ground unused; tie to ground rxval[3] input unused; tie to ground unused; tie to ground rxerr[3] input unused; tie to ground unused; tie to ground rxprty[3] input unused; tie to ground unused; tie to ground rxfa[3] input unused; tie to ground unused; tie to ground port 2 (sphy) rxclk23 input rxclk23 txclk23 rxenb[2] output rxenb[2] txfa[2] rxsof[2] input rxsof[2] txsof[2] rxeof[2] input rxeof[2] txeof[2] rxval[2] input rxval[2] txenb[2] rxerr[2] input rxerr[2] txerr[2] rxprty[2] input rxprty[2] txprty[2] rxfa[2] input rxfa[2] unused; tie to ground rxpadl[1] input rxpadl[1] txpadl[1] rxdata[31:16] input rxdata[31:16] txdata[31:16] port 1 (unused) rxclk01 input rxclk01 txclk01 rxsof[1] input unused; tie to ground unused; tie to ground rxeof[1] input unused; tie to ground unused; tie to ground rxval[1] input unused; tie to ground unused; tie to ground rxerr[1] input unused; tie to ground unused; tie to ground rxprty[1] input unused; tie to ground unused; tie to ground rxfa[1] input unused; tie to ground unused; tie to ground table 13. 1x32 csix mode (continued) port master pin name direction notes
intel ? IXP2400 network processor datasheet 45 port 0 (mphy) rxclk01 input rxclk01 mphy slave mode is not supported rxenb[0] output rxenb[0] rxsof[0] input rxsof[0] rxeof[0] input unused, tie to ground rxval[0] input unused; tie to ground rxerr[0] input unused, tie to ground rxprty[0] input rxprty[0] rxfa[0] input unused, tie to ground rxpadl[0] input unused, tie to ground rxdata[15:0] input rxdata[15:0] txcsrb output rxaddr[4] rxaddr[3:0] output rxaddr[3:0] rxpfa input rxpfa port 3 (unused) txclk23 input txclk23 rxclk23 txenb[3] output unused; no connect unused; no connect txsof[3] output unused; no connect unused; no connect txeof[3] output unused; no connect unused; no connect txerr[3] output unused; no connect unused; no connect txprty[3] output unused; no connect unused; no connect txfa[3] input unused; tie to ground unused; tie to ground port 2 (sphy) txclk23 input txclk23 rxclk23 txenb[2] output txenb[2] rxval[2] txsof[2] output txsof[2] rxsof[2] txeof[2] output txeof[2] rxeof[2] txerr[2] output txerr[2] rxerr[2] txprty[2] output txprty[2] rxprty[2] txfa[2] input txfa[2] rxenb[2] txpadl[1] output txpadl[1] rxpadl[1] txdata[31:16] output txdata[31:16] rxdata[31:16] port 1 (unused) txclk01 input txclk01 rxclk01 txsof[1] output unused; no connect unused; no connect txeof[1] output unused; no connect unused; no connect txerr[1] output unused; no connect unused; no connect txprty[1] output unused; no connect unused; no connect txfa[1] input unused; tie to ground unused; tie to ground table 14. x16 utopia level 2 mphy-32 + x16 sphy (utopia or pos-phy) mode (continued) port pin name direction master mode function and description slave mode function and description
intel ? IXP2400 network processor 46 datasheet port 0 (mphy) txclk01 input txclk01 mphy slave mode is not supported txenb[0] output txenb[0] txsof[0] output txsof[0] txeof[0] output unused; no connect txerr[0] output unused; no connect txprty[0] output txprty[0] txfa[0] input unused; tie to ground txpadl[0] output unused; no connect txdata[15:0] output txdata[15:0] txpfa input txpfa txsfa input unused; no connect txenb[1] output txaddr[4] txaddr[3:0] output txaddr[3:0] table 15. x16 utopia level 2 mphy-32 + 2x8 sphy (utopia or pos-phy) mode port pin name direction master mode function and description slave mode function and description port 3 (sphy) rxclk23 input rxclk23 txclk23 rxenb[3] output rxenb[3] txfa[3] rxsof[3] input rxsof[3] txsof[3] rxeof[3] input rxeof[3] txeof[3] rxval[3] input rxval[3] txenb[3] rxerr[3] input rxerr[3] txerr[3] rxprty[3] input rxprty[3] txprty[3] rxfa[3] input rxfa[3] unused; tie to ground rxdata[31:24] input rxdata[31:24] txdata[31:24] table 14. x16 utopia level 2 mphy-32 + x16 sphy (utopia or pos-phy) mode (continued) port pin name direction master mode function and description slave mode function and description
intel ? IXP2400 network processor datasheet 47 port 2 (sphy) rxclk23 input rxclk23 txclk23 rxenb[2] output rxenb[2] txfa[2] rxsof[2] input rxsof[2] txsof[2] rxeof[2] input rxeof[2] txeof[2] rxval[2] input rxval[2] txenb[2] rxerr[2] input rxerr[2] txerr[2] rxprty[2] input rxprty[2] txprty[2] rxfa[2] input rxfa[2] unused; tie to ground rxpadl[1] input unused; tie to ground unused; tie to ground rxdata[23:16] input rxdata[23:16] txdata[23:16] port 1 (unused) rxclk01 input rxclk01 txclk01 rxsof[1] input unused; tie to ground unused; tie to ground rxeof[1] input unused; tie to ground unused; tie to ground rxval[1] input unused; tie to ground unused; tie to ground rxerr[1] input unused; tie to ground unused; tie to ground rxprty[1] input unused; tie to ground unused; tie to ground rxfa[1] input unused; tie to ground unused; tie to ground port 0 (mphy) rxclk01 input rxclk01 mphy slave mode is not supported rxenb[0] output rxenb[0] rxsof[0] input rxsof[0] rxeof[0] input unused, tie to ground rxval[0] input unused; tie to ground rxerr[0] input unused, tie to ground rxprty[0] input rxprty[0] rxfa[0] input unused, tie to ground rxpadl[0] input unused, tie to ground rxdata[15:0] input rxdata[15:0] txcsrb output rxaddr[4] rxaddr[3:0] output rxaddr[3:0] rxpfa input rxpfa table 15. x16 utopia level 2 mphy-32 + 2x8 sphy (utopia or pos-phy) mode (continued) port pin name direction master mode function and description slave mode function and description
intel ? IXP2400 network processor 48 datasheet port 3 (sphy) txclk23 input txclk23 rxclk23 txenb[3] output txenb[3] rxval[3] txsof[3] output txsof[3] rxsof[3] txeof[3] output txeof[3] rxeof[3] txerr[3] output txerr[3] rxerr[3] txprty[3] output txprty[3] rxprty[3] txfa[3] input txfa[3] rxenb[3] txdata[31:24] output txdata[31:24] rxdata[31:24] port 2 (sphy) txclk23 input txclk23 rxclk23 txenb[2] output txenb[2] rxval[2] txsof[2] output txsof[2] rxsof[2] txeof[2] output txeof[2] rxeof[2] txerr[2] output txerr[2] rxerr[2] txprty[2] output txprty[2] rxprty[2] txfa[2] input txfa[2] rxenb[2] txpadl[1] output unused; tie to ground unused; tie to ground txdata[23:16] output txdata[23:16] rxdata[23:16] port 1 (unused) txclk01 input txclk01 rxclk01 txsof[1] output unused; no connect unused; no connect txeof[1] output unused; no connect unused; no connect txerr[1] output unused; no connect unused; no connect txprty[1] output unused; no connect unused; no connect txfa[1] input unused; tie to ground unused; tie to ground port 0 (mphy) txclk01 input txclk01 mphy slave mode is not supported txenb[0] output txenb[0] txsof[0] output txsof[0] txeof[0] output unused; no connect txerr[0] output unused; no connect txprty[0] output txprty[0] txfa[0] input unused; tie to ground txpadl[0] output unused; no connect txdata[15:0] output txdata[15:0] txpfa input txpfa txsfa input unused; no connect txenb[1] output txaddr[4] txaddr[3:0] output txaddr[3:0] table 15. x16 utopia level 2 mphy-32 + 2x8 sphy (utopia or pos-phy) mode (continued) port pin name direction master mode function and description slave mode function and description
intel ? IXP2400 network processor datasheet 49 table 16. x16 pos-phy level 2 mphy-32 + x16 sphy (utopia or pos-phy) mode port pin name direction master mode function and description slave mode function and description port 3 (unused) rxclk23 input rxclk23 txclk23 rxenb[3] output unused; no connect unused, no connect rxsof[3] input unused; tie to ground unused; tie to ground rxeof[3] input unused; tie to ground unused; tie to ground rxval[3] input unused; tie to ground unused; tie to ground rxerr[3] input unused; tie to ground unused; tie to ground rxprty[3] input unused; tie to ground unused; tie to ground rxfa[3] input unused; tie to ground unused; tie to ground port 2 (sphy) rxclk23 input rxclk23 txclk23 rxenb[2] output rxenb[2] txfa[2] rxsof[2] input rxsof[2] txsof[2] rxeof[2] input rxeof[2] txeof[2] rxval[2] input rxval[2] txenb[2] rxerr[2] input rxerr[2] txerr[2] rxprty[2] input rxprty[2] txprty[2] rxfa[2] input rxfa[2] unused; tie to ground rxpadl[1] input rxpadl[1] txpadl[1] rxdata[31:16] input rxdata[31:16] txdata[31:16] port 1 (unused) rxclk01 input rxclk01 txclk01 rxsof[1] input unused; tie to ground unused; tie to ground rxeof[1] input unused; tie to ground unused; tie to ground rxval[1] input unused; tie to ground unused; tie to ground rxerr[1] input unused; tie to ground unused; tie to ground rxprty[1] input unused; tie to ground unused; tie to ground rxfa[1] input unused; tie to ground unused; tie to ground
intel ? IXP2400 network processor 50 datasheet port 0 (mphy) rxclk01 input rxclk01 mphy slave mode is not supported rxenb[0] output rxenb[0] rxsof[0] input rxsof[0] rxeof[0] input rxeof[0] rxval[0] input rxval[0] rxerr[0] input rxerr[0] rxprty[0] input rxprty[0] rxfa[0] input unused, tie to ground rxpadl[0] input rxpadl[0] rxdata[15:0] input rxdata[15:0] txcsrb output rxaddr[4] rxaddr[3:0] output rxaddr[3:0] rxpfa input rxpfa port 3 (unused) txclk23 input txclk23 rxclk23 txenb[3] output unused; no connect unused; no connect txsof[3] output unused; no connect unused; no connect txeof[3] output unused; no connect unused; no connect txerr[3] output unused; no connect unused; no connect txprty[3] output unused; no connect unused; no connect txfa[3] input unused; tie to ground unused; tie to ground port 2 (sphy) txclk23 input txclk23 rxclk23 txenb[2] output txenb[2] rxval[2] txsof[2] output txsof[2] rxsof[2] txeof[2] output txeof[2] rxeof[2] txerr[2] output txerr[2] rxerr[2] txprty[2] output txprty[2] rxprty[2] txfa[2] input txfa[2] rxenb[2] txpadl[1] output txpadl[1] rxpadl[1] txdata[31:16] output txdata[31:16] rxdata[31:16] port 1 (unused) txclk01 input txclk01 rxclk01 txsof[1] output unused; no connect unused; no connect txeof[1] output unused; no connect unused; no connect txerr[1] output unused; no connect unused; no connect txprty[1] output unused; no connect unused; no connect txfa[1] input unused; tie to ground unused; tie to ground table 16. x16 pos-phy level 2 mphy-32 + x16 sphy (utopia or pos-phy) mode (continued) port pin name direction master mode function and description slave mode function and description
intel ? IXP2400 network processor datasheet 51 port 0 (mphy) txclk01 input txclk01 mphy slave mode is not supported txenb[0] output txenb[0] txsof[0] output txsof[0] txeof[0] output txeof[0] txerr[0] output txerr[0] txprty[0] output txprty[0] txfa[0] input unused; tie to ground txpadl[0] output txpadl[0] txdata[15:0] output txdata[15:0] txpfa input txpfa txsfa input txsfa txenb[1] output txaddr[4] txaddr[3:0] output txaddr[3:0] table 17. x16 pos-phy level 2 mphy-32 + 2x8 sphy (utopia or pos-phy) mode port pin name direction master mode function and description slave mode function and description port 3 (sphy) rxclk23 input rxclk23 txclk23 rxenb[3] output rxenb[3] txfa[3] rxsof[3] input rxsof[3] txsof[3] rxeof[3] input rxeof[3] txeof[3] rxval[3] input rxval[3] txenb[3] rxerr[3] input rxerr[3] txerr[3] rxprty[3] input rxprty[3] txprty[3] rxfa[3] input rxfa[3] unused; tie to ground rxdata[31:24] input rxdata[31:24] txdata[31:24] table 16. x16 pos-phy level 2 mphy-32 + x16 sphy (utopia or pos-phy) mode (continued) port pin name direction master mode function and description slave mode function and description
intel ? IXP2400 network processor 52 datasheet port 2 (sphy) rxclk23 input rxclk23 txclk23 rxenb[2] output rxenb[2] txfa[2] rxsof[2] input rxsof[2] txsof[2] rxeof[2] input rxeof[2] txeof[2] rxval[2] input rxval[2] txenb[2] rxerr[2] input rxerr[2] txerr[2] rxprty[2] input rxprty[2] txprty[2] rxfa[2] input rxfa[2] unused; tie to ground rxpadl[1] input unused; tie to ground unused; tie to ground rxdata[23:16] input rxdata[23:16] txdata[23:16] port 1 (unused) rxclk01 input rxclk01 txclk01 rxsof[1] input unused; tie to ground unused; tie to ground rxeof[1] input unused; tie to ground unused; tie to ground rxval[1] input unused; tie to ground unused; tie to ground rxerr[1] input unused; tie to ground unused; tie to ground rxprty[1] input unused; tie to ground unused; tie to ground rxfa[1] input unused; tie to ground unused; tie to ground port 0 (mphy) rxclk01 input rxclk01 mphy slave mode is not supported rxenb[0] output rxenb[0] rxsof[0] input rxsof[0] rxeof[0] input rxeof[0] rxval[0] input rxval[0] rxerr[0] input rxerr[0] rxprty[0] input rxprty[0] rxfa[0] input unused, tie to ground rxpadl[0] input rxpadl[0] rxdata[15:0] input rxdata[15:0] txcsrb output rxaddr[4] rxaddr[3:0] output rxaddr[3:0] rxpfa input rxpfa table 17. x16 pos-phy level 2 mphy-32 + 2x8 sphy (utopia or pos-phy) mode (continued) port pin name direction master mode function and description slave mode function and description
intel ? IXP2400 network processor datasheet 53 port 3 (sphy) txclk23 input txclk23 rxclk23 txenb[3] output txenb[3] rxval[3] txsof[3] output txsof[3] rxsof[3] txeof[3] output txeof[3] rxeof[3] txerr[3] output txerr[3] rxerr[3] txprty[3] output txprty[3] rxprty[3] txfa[3] input txfa[3] rxenb[3] txdata[31:24] output txdata[31:24] rxdata[31:24] port 2 (sphy) txclk23 input txclk23 rxclk23 txenb[2] output txenb[2] rxval[2] txsof[2] output txsof[2] rxsof[2] txeof[2] output txeof[2] rxeof[2] txerr[2] output txerr[2] rxerr[2] txprty[2] output txprty[2] rxprty[2] txfa[2] input txfa[2] rxenb[2] txpadl[1] output unused; tie to ground unused; tie to ground txdata[23:16] output txdata[23:16] rxdata[23:16] port 1 (unused) txclk01 input txclk01 rxclk01 txsof[1] output unused; no connect unused; no connect txeof[1] output unused; no connect unused; no connect txerr[1] output unused; no connect unused; no connect txprty[1] output unused; no connect unused; no connect txfa[1] input unused; tie to ground unused; tie to ground port 0 (mphy) txclk01 input txclk01 mphy slave mode is not supported txenb[0] output txenb[0] txsof[0] output txsof[0] txeof[0] output txeof[0] txerr[0] output txerr[0] txprty[0] output txprty[0] txfa[0] input unused; tie to ground txpadl[0] output txpadl[0] txdata[15:0] output txdata[15:0] txpfa input txpfa txsfa input txsfa txenb[1] output txaddr[4] txaddr[3:0] output txaddr[3:0] table 17. x16 pos-phy level 2 mphy-32 + 2x8 sphy (utopia or pos-phy) mode (continued) port pin name direction master mode function and description slave mode function and description
intel ? IXP2400 network processor 54 datasheet table 18. 1x32 sphy slave mode port master pin name direction slave mode function and description port 3 (unused) rxclk23 input unused; tie to ground rxenb[3] output unused; no connect rxsof[3] input unused; tie to ground rxeof[3] input unused; tie to ground rxval[3] input unused; tie to ground rxerr[3] input unused; tie to ground rxprty[3] input unused; tie to ground rxfa[3] input unused; tie to ground port 2 (unused) rxclk23 input unused; tie to ground rxenb[2] output unused; no connect rxsof[2] input unused; tie to ground rxeof[2] input unused; tie to ground rxval[2] input unused; tie to ground rxerr[2] input unused; tie to ground rxprty[2] input unused; tie to ground rxfa[2] input unused; tie to ground port 1 (unused) rxclk01 input txclk01 rxenb[1] output unused; no connect rxsof[1] input unused; tie to ground rxeof[1] input unused; tie to ground rxval[1] input unused; tie to ground rxerr[1] input unused; tie to ground rxprty[1] input unused; tie to ground rxfa[1] input unused; tie to ground port 0 rxclk01 input txclk01 rxenb[0] output txfa[0] rxsof[0] input txsof[0] rxeof[0] input txeof[0] rxval[0] input txenb[0] rxerr[0] input txerr[0] rxprty[0] input txprty[0] rxfa[0] input unused; tie to ground rxdata[31:0] input txdata[31:0] rxpadl[1:0] input txpadl[1:0] mphy (unused) rxaddr[3:0] output unused; no connect rxpfa input unused; tie to ground
intel ? IXP2400 network processor datasheet 55 port 3 (unused) txclk23 input unused; tie to ground txenb[3] output unused; no connect txsof[3] output unused; no connect txeof[3] output unused; no connect txerr[3] output unused; no connect txprty[3] output unused; no connect txfa[3] input unused; tie to ground port 2 (unused) txclk23 input unused; tie to ground txenb[2] output unused; no connect txsof[2] output unused; no connect txeof[2] output unused; no connect txerr[2] output unused; no connect txprty[2] output unused; no connect txfa[2] input unused; tie to ground port 1 (unused) txclk01 input rxclk01 txenb[1] output unused; no connect txsof[1] output unused; no connect txeof[1] output unused; no connect txerr[1] output unused; no connect txprty[1] output unused; no connect txfa[1] input unused; tie to ground port 0 txclk01 input rxclk01 txenb[0] output rxval[0] txsof[0] output rxsof[0] txeof[0] output rxeof[0] txerr[0] output rxerr[0] txprty[0] output rxprty[0] txfa[0] input rxenb[0] txpadl[1:0] output rxpadl[1:0] txdata[31:0] output rxdata[31:0] mphy (unused) txpfa input unused; tie to ground txsfa input unused; tie to ground txaddr[3:0] output unused; no connect table 18. 1x32 sphy slave mode (continued) port master pin name direction slave mode function and description
intel ? IXP2400 network processor 56 datasheet table 19. 2x16 sphy slave mode port master pin name direction slave mode function and description port 3 (unused) rxclk23 input txclk23 rxenb[3] output unused; no connect rxsof[3] input unused; tie to ground rxeof[3] input unused; tie to ground rxval[3] input unused; tie to ground rxerr[3] input unused; tie to ground rxprty[3] input unused; tie to ground rxfa[3] input unused; tie to ground port 2 rxclk23 input txclk23 rxenb[2] output txfa[2] rxsof[2] input txsof[2] rxeof[2] input txeof[2] rxval[2] input txenb[2] rxerr[2] input txerr[2] rxprty[2] input txprty[2] rxfa[2] input unused; tie to ground rxpadl[1] input txpadl[1]; port 2 rxdata[31:16] input txdata[31:16]; port 2 transmit data port 1 rxclk01 input txclk01 rxenb[1] output unused; no connect rxsof[1] input unused; tie to ground rxeof[1] input unused; tie to ground rxval[1] input unused; tie to ground rxerr[1] input unused; tie to ground rxprty[1] input unused; tie to ground rxfa[1] input unused; tie to ground port 0 rxclk01 input txclk01 rxenb[0] output txfa[0] rxsof[0] input txsof[0] rxeof[0] input txeof[0] rxval[0] input txenb[0] rxerr[0] input txerr[0] rxprty[0] input txprty[0] rxfa[0] input unused; tie to ground rxpadl[0] input txpadl[0]; port 0 rxdata[15:0] input txdata[15:0]; port 0 transmit data
intel ? IXP2400 network processor datasheet 57 mphy (unused) rxaddr[3:0] output unused; no connect rxpfa input unused; tie to ground port 3 (unused) txclk23 input rxclk23 txenb[3] output unused; no connect txsof[3] output unused; no connect txeof[3] output unused; no connect txerr[3] output unused; no connect txprty[3] output unused; no connect txfa[3] input unused; tie to ground port 2 txclk23 input rxclk23 txenb[2] output rxval[2] txsof[2] output rxsof[2] txeof[2] output rxeof[2] txerr[2] output rxerr[2] txprty[2] output rxprty[2] txfa[2] input rxenb[2] txpadl[1] output rxpadl[1]; port 2 txdata[31:16] output rxdata[31:16]; port 2 receive data port 1 (unused) txclk01 input rxclk01 txenb[1] output unused; no connect txsof[1] output unused; no connect txeof[1] output unused; no connect txerr[1] output unused; no connect txprty[1] output unused; no connect txfa[1] input unused; tie to ground port 0 txclk01 input rxclk01 txenb[0] output rxval[0] txsof[0] output rxsof[0] txeof[0] output rxeof[0] txerr[0] output rxerr[0] txprty[0] output rxprty[0] txfa[0] input rxenb[0] txpadl[0] output rxpadl[0]; port 0 txdata[15:0] output rxdata[15:0]; port 0 receive data mphy (unused) txpfa input unused; tie to ground txsfa input unused; tie to ground txaddr[3:0] output unused; no connect table 19. 2x16 sphy slave mode (continued) port master pin name direction slave mode function and description
intel ? IXP2400 network processor 58 datasheet table 20. 4x8 sphy slave mode port master pin name direction slave mode function and description port 3 rxclk23 input txclk23 rxenb[3] output txfa[3] rxsof[3] input txsof[3] rxeof[3] input txeof[3] rxval[3] input txenb[3] rxerr[3] input txerr[3] rxprty[3] input txprty[3] rxfa[3] input unused; tie to ground rxdata[31:24] input txdata[31:24]; port 3 transmit data port 2 rxclk23 input txclk23 rxenb[2] output txfa[2] rxsof[2] input txsof[2] rxeof[2] input txeof[2] rxval[2] input txenb[2] rxerr[2] input txerr[2] rxprty[2] input txprty[2] rxfa[2] input unused; tie to ground rxpadl[1] input unused; tie to ground rxdata[23:16] input txdata[23:16]; port 2 transmit data port 1 rxclk01 input txclk01 rxenb[1] output txfa[3] rxsof[1] input txsof[1] rxeof[1] input txeof[1] rxval[1] input txenb[1] rxerr[1] input txerr[1] rxprty[1] input txprty[1] rxfa[1] input unused; tie to ground rxdata[15:8] input txdata[15:8]; port 1 transmit data
intel ? IXP2400 network processor datasheet 59 port 0 rxclk01 input txclk01 rxenb[0] output txfa[0] rxsof[0] input txsof[0] rxeof[0] input txeof[0] rxval[0] input txenb[0] rxerr[0] input txerr[0] rxprty[0] input txprty[0] rxfa[0] input unused; tie to ground rxpadl[0] input unused; tie to ground rxdata[7:0] input txdata[7:0]; port 0 transmit data mphy (unused) rxaddr[3:0] output unused; no connect rxpfa input unused; tie to ground port 3 txclk23 input rxclk23 txenb[3] output rxval[3] txsof[3] output rxsof[3] txeof[3] output rxeof[3] txerr[3] output rxerr[3] txprty[3] output rxprty[3] txfa[3] input rxenb[3] txdata[31:24] output rxdata[31:24]; port 3 receive data port 2 txclk23 input rxclk23 txenb[2] output rxval[2] txsof[2] output rxsof[2] txeof[2] output rxeof[2] txerr[2] output rxerr[2] txprty[2] output rxprty[2] txfa[2] input rxenb[2] txpadl[0] output unused; no connect txdata[23:16] output rxdata[23:16]; port 2 receive data port 1 txclk01 input rxclk01 txenb[1] output rxval[1] txsof[1] output rxsof[1] txeof[1] output rxeof[1] txerr[1] output rxerr[1] txprty[1] output rxprty[1] txfa[1] input rxenb[1] txdata[15:8] output rxdata[15:8]; port 1 receive data table 20. 4x8 sphy slave mode (continued) port master pin name direction slave mode function and description
intel ? IXP2400 network processor 60 datasheet port 0 txclk01 input rxclk01 txenb[0] output rxval[0] txsof[0] output rxsof[0] txeof[0] output rxeof[0] txerr[0] output rxerr[0] txprty[0] output rxprty[0] txfa[0] input rxenb[0] txpadl[0] output unused; no connect txdata[7:0] output rxdata[7:0]; port 0 receive data mphy (unused) txpfa input unused; tie to ground txsfa input unused; tie to ground txaddr[3:0] output unused; no connect table 21. 1x16+2x8 sphy slave mode port master pin name direction slave mode function and description port 3 rxclk23 input txclk23 rxenb[3] output txfa[3] rxsof[3] input txsof[3] rxeof[3] input txeof[3] rxval[3] input txenb[3] rxerr[3] input txerr[3] rxprty[3] input txprty[3] rxfa[3] input unused; tie to ground rxdata[31:24] input txdata[31:24]; port 3 transmit data port 2 rxclk23 input txclk23 rxenb[2] output txfa[2] rxsof[2] input txsof[2] rxeof[2] input txeof[2] rxval[2] input txenb[2] rxerr[2] input txerr[2] rxprty[2] input txprty[2] rxfa[2] input unused; tie to ground rxpadl[1] input unused; tie to ground rxdata[23:16] input txdata[23:16]; port 2 transmit data table 20. 4x8 sphy slave mode (continued) port master pin name direction slave mode function and description
intel ? IXP2400 network processor datasheet 61 port 1 (unused) rxclk01 input txclk01 rxenb[1] output unused; no connect rxsof[1] input unused; tie to ground rxeof[1] input unused; tie to ground rxval[1] input unused; tie to ground rxerr[1] input unused; tie to ground rxprty[1] input unused; tie to ground rxfa[1] input unused; tie to ground port 0 rxclk01 input txclk01 rxenb[0] output txfa[0] rxsof[0] input txsof[0] rxeof[0] input txeof[0] rxval[0] input txenb[0] rxerr[0] input txerr[0] rxprty[0] input txprty[0] rxfa[0] input unused; tie to ground rxpadl[0] input txpadl[0]; port 0 rxdata[15:0] input txdata[15:0]; port 0 transmit data mphy (unused) rxaddr[3:0] output unused; no connect rxpfa input unused; tie to ground port 3 txclk23 input rxclk23 txenb[3] output rxval[3] txsof[3] output rxsof[3] txeof[3] output rxeof[3] txerr[3] output rxerr[3] txprty[3] output rxprty[3] txfa[3] input rxenb[3] txdata[31:24] output rxdata[31:24]; port 3 receive data port 2 txclk23 input rxclk23 txenb[2] output rxval[2] txsof[2] output rxsof[2] txeof[2] output rxeof[2] txerr[2] output rxerr[2] txprty[2] output rxprty[2] txfa[2] input rxenb[2] txpadl[1] output unused; no connect txdata[23:16] output rxdata[23:16]; port 2 receive data table 21. 1x16+2x8 sphy slave mode (continued) port master pin name direction slave mode function and description
intel ? IXP2400 network processor 62 datasheet port 1 (unused) txclk01 input rxclk01 txenb[1] output unused; no connect txsof[1] output unused; no connect txeof[1] output unused; no connect txerr[1] output unused; no connect txprty[1] output unused; no connect txfa[1] input unused; tie to ground port 0 txclk01 input rxclk01 txenb[0] output rxval[0] txsof[0] output rxsof[0] txeof[0] output rxeof[0] txerr[0] output rxerr[0] txprty[0] output rxprty[0] txfa[0] input rxenb[0] txpadl[0] output rxpadl[0]; port 0 txdata[15:0] output rxdata[31:0]; port 0 receive data mphy (unused) txpfa input unused; tie to ground txsfa input unused; tie to ground txaddr[3:0] output unused; no connect table 22. cbus pinout pin name direction description txcdata[3:0] output transmit data txcdata[7:4] output additonal 4 bits to double the cb us width, these pins are muxed on rxaddr[3:0] as shown in table 13 . txcsof output transmit start of frame txcsrb output transmit serialized ready bits txcfc input transmit flow control fifo full txcpar output transmit parity for txcdata[3:0] rxcdata[3:0] input receive data rxcdata[7:4] input additonal 4 bits to double the cb us width, these pins are muxed on txfa[1], txfa[0], txpfa, txsfa respectively as shown in table 13 . rxcsof input receive start of frame rxcsrb input receive serialized ready bits rxcfc output receive flow control fifo full rxcpar input receive parity table 21. 1x16+2x8 sphy slave mode (continued) port master pin name direction slave mode function and description
intel ? IXP2400 network processor datasheet 63 3.2.4 pci pci bus can be used to interface to industry-s tandard io devices, or to a host processor. see table 23 for a list of signals. pci signaling levels are defined in pci rev. 2.2 specification. table 23. pci signals signal name i/o description number pci_clk i clock input for the pci core clock domain (0 to 66 mhz) 1 pci_ad[63:0] io multiplexed address/data bus 64 pci_cbe_l[7:0] io command and byte enable bus 8 pci_rst_l io active-low pci reset signal. this is an output if IXP2400 is the bus host. it is an input if IXP2400 is not the bus host. the direction of this pin is controlled by the cfg_rstdir pin. 1 pci_inta_l io receives interrupt from another pci device if the IXP2400 is the bus host; ot herwise used as an interrupt to the host processor. 1 pci_intb_l i receives interrupt from another pci device if the IXP2400 is the bus host. 1 pci_frame_l io transaction in progress indication 1 pci_stop_l io termination with retry or disconnect-with-data 1 pci_irdy_l io initiator ready on data phase 1 pci_trdy_l io target ready on data phase 1 pci_devsel_l io device select indication 1 pci_idsel i idsel signal to the IXP2400; used during the configuration cycle 1 pci_req_l[0] io bus requests from external master 0, used when the IXP2400 is arbiter/host; the IXP2400?s request output to external arbiter when not a host. 1 pci_req_l[1] i bus requests from external master 1, used when the IXP2400 is arbiter/host. 1 pci_gnt_l[0] io bus grant output to external master 0 when this chip is arbiter/host; grant input to the IXP2400 from external arbiter when not a host. 1 pci_gnt_l[1] o bus grants to external master 1, used when the IXP2400 is arbiter/host 1 pci_req64_l io indication that a 64-bit data phase is desired. during reset, driven low by the system to indicate 64-bit capability. 1 pci_ack64_l io indicates that a 64-bit data phase is accepted. 1 pci_par io parity on ad[31:0] 1 pci_par64 io parity on ad[63:32] 1 pci_perr_l io parity error detected on incoming data 1 pci_serr_l io parity error on address phase, illegal command, etc. when this chip is the host serr is an input; when using with an external host, serr is an output. 1 pci_rcomp i buffer compensation 1 1 total (per channel) 93
intel ? IXP2400 network processor 64 datasheet 3.2.5 slowport signals the slowport is used to interface to asynchron ous devices. typically this will be a flash rom (boot rom) and maintenance port of mac devices. see table 24 . 3.2.6 gpio signals gpio are general-purpose io signals. they can be used for slow-speed, software-controlled io such as leds and input switches. they are also tri-stated during reset to bring configuration information into the IXP2400; this information is latched at the deassertion of reset. gpios use lvttl signalling (3.3v); see table 25 . 1. the pci_rcomp pin should be connected to ground through external a 24 ? 1% resistor and one 0603 0.1 f decoupling capacitor. place the resistor and capacitor as close to the IXP2400 as possible, within 1.0? of the package. the compensation signal should be routed with as wide a trace as possible, minimum of 12 mils wide and isolated from other signals with a min- imum of 10-mil spacing. table 24. slowport signals signal name i/o description number sp_clk 1 1. sp_clk can drive a maximum of two loads, 10 pf each. o this clock is used to time all the external slowport transfers. it can be adjusted by the ccr register. the ccr contains the clock divisor information. this clock is generated by dividing the shxp_apb_clk . 1 sp_wr_l o write strobe to indicate the write access to the prom bus. 1 sp_rd_l o read strobe to indicate the read access from the prom bus. 1 sp_ad[7:0] io address and data multiplexed bidirectional tri-state bus. 8 sp_ack_l i acknowledge signal responded by the prom devices when the transaction is complete.for special application, this pin acts as interrupt input from the external device. 1 sp_cs_l[1:0] o device select signals to indicate which device will be addressed. 2 sp_ale_l o address latch enable signal to indicate the address is placed in the prom bus. 1 sp_cp_sp_a[0] o latches consecutive bytes ont o external buffers. used for 16,32-bit data bus device only. also acts as an address [0] signal during the mode 0 set in th e protocol control register for 8-bit device transaction. 1 sp_oe_l o shifts the bytes out of the external buffers. 1 sp_dir_sp_a[1] o controls the direction of the data transaction. for read, it is asserted low; for write, it is asserted high. also acts as an address [1] signal during the mode 0 set in the protocol control register for the 8-bit device transaction. 1 total (per channel) 18
intel ? IXP2400 network processor datasheet 65 3.2.7 serial port signals serial port is the rs-232?compatible uart used for debug and diagnostics. see table 26 . 3.2.8 clock signals table 27 lists the clock and reset signals. 3.2.9 test, jtag, and miscellaneous signals jtag is the ieee 1149.1 test access port. the jtag input signals have a weak pull-up resistor internal to the chip, so that any input not terminated will be interpreted as a high. other test signals are IXP2400?specific for manufacturing use only. see table 28 . table 25. gpio signals signal name i/o description number gpio[7:0] io general-purpose io 8 total (per channel) 8 table 26. serial port signals signal name i/o description number serial_rx i receive data into the uart 1 serial_tx o transmit data from the uart 1 total (per channel) 2 table 27. clock signals signal name i/o description number sys_clk i system clock this is the core pll reference clock; nominally 100 mhz 1 sys_reset_l i system reset input if the IXP2400 is on an externally hosted pci system this is connected to pci_rst_l 1 sys_reset_out_l o reset out IXP2400 output to reset the other board devices 1 total (per channel) 3
intel ? IXP2400 network processor 66 datasheet table 28. test, jtag, and miscellaneous signals signal name i/o description number tck i test interface reference clock. this clock times all the transfers on the jtag test interface. 1 tms_t_clk i when t_load = 0 this pin functions as the jtag test mode select pin. when t_load = 1 this pin functions as the test logic test clock, used to capture test mode data from gpio and slowport pins into the test box. 1 tdi_t_scan_en i when t_load = 0 this pin functions as the jtag test data in pin. when t_load = 1 this pin functions as the test logic scan enable, configuring the internal flip-flops into scan chains. 1 tdo o test interface data output. tdo is the serial output through which test instructions and data from the test logic leave the IXP2400. 1 trst_l i test interface reset. when asserted low, the tap controller is asynchronously forced to enter a reset state, which in turn asynchronously initializes other test logic. this pin must be driven or held low to achieve normal device operation. 1 t_sys_refclk i test system reference clock (for debug only) this input is xor?ed with sys_clk so that a 2x clock can be generated when the pll is bypassed; for normal operation tie to gnd. 1 t_load i test load 1- selects signals from the gpio and slowport pins to be routed to the test box instead of the gpio and slowport ports, and sets the tms/t_clk and tdi/t_scan_en pins to operate in their test mode. 0 - these pins have their normal function. 1 t_diag_clk i memory bist diagnostic clock this clock is used to shift out failing data from the memory bist controllers during the debug mode. 1 thermda 1 i thermal diode anode. if unused, this pin does not need to be connected. 1 thermdc 1 i thermal diode cathode. if unused, this pin does not need to be connected. 1 pll_bypass i system pll bypass select 0 - use core pll output as core clock 1 - use sys_clk as core clock for normal operation, connect to 0. 1 pll_div_bypass i pll divider bypass 0 - core pll divider block is not bypassed in a system board this pin should be held low. if set high, the IXP2400 may not operate properly. 1 tst_reset_l i indicates that power has reached a certain level. keep pulled-up for normal operation. 1 vcca analog clock power 1 vssa 1 vcc3_3 3.3 v i/o power 1
intel ? IXP2400 network processor datasheet 67 3.2.10 configuration pins these pins are tied statically high or low through a resistor to provide configuration information into the IXP2400 at reset. for all but cfg_rst_dir, these pins are used for other purposes after reset. for those pins the configuration information is sampled at the deassertion edge of reset. the values sampled can be read in the strap_options register. vcc2_5 2.5 v ddr i/o power 1 vcc1_5 1_5 v qdr i/o power 1 total (per channel) 18 1. for these signals, the thermal equation used to convert voltage to temperature is: y = -551.225x + 410.694 for example, if the voltage is 0.53, then y = -551.225 * .53 + 410.694 = 118c table 28. test, jtag, and miscellaneous signals (continued) signal name i/o description number table 29. configuration/gpio pins (sheet 1 of 2) signal name i/o configuration function description number cfg_rstdir io cfg_rst_dir 1?IXP2400 is the host supporting central functions IXP2400 will drive pci_rst_l (output). IXP2400 will drive pci_req64_l low during pci reset. IXP2400 will drive pci_ad[31:0], pci_be[3:0] and par low during pci reset 0?there is an external pci host supporting the central functions. pci_rst_l is an input pci_req64_l is an input during reset. pci_ad[31:0], pci_be[3:0] and pci_par are tristated during pci reset. 1 gpio[0] io cfg_prom_ boot indicates if boot rom is present 0?no boot rom; host must download boot image into dram 1?boot rom is present 1 gpio[1] io cfg_pci_boot_ host indicates if host or the intel xscale core will configure pci devices 0? external host 1?IXP2400 network processor 1 gpio[2] io cfg_pci_arb pci arbiter used 0?external arbiter 1?internal arbiter 1 gpio[4:3] io cfg_pci_ dwin[1:0] select dram bar window size 11?1024 mbyte 10?512 mbyte 01?256 mbyte 00?128 mbyte 2
intel ? IXP2400 network processor 68 datasheet 3.2.11 pin state during reset in addition to the configuration pins listed in table 29 , at the deassertion edge of the reset tst_reset_l must always be tied high. 3.3 power supply sequencing 3.3.1 power-up sequence the IXP2400 has the following power supplies: 1. vcc3.3 3.3v power supply for the media switch fabric interface, pci, gpio, slowport and misc. 2. vcc and vcca 1.3v power supply for the core and for the pll 3. vcc2.5 2.5v power supply for the ddr dram 4. vcc1.5 1.5v power supply for the qdr sram 5. d_vref 1.25v for the ddr dram 6. sn_vref 0.75v for qdr sram channel 0, and channel 1 the power supplies for the IXP2400 should be brought up in a controlled sequence. the delay between the power-up of the power supplies should be 5 ms or less (min is 50 s); there is no dependency between the sequence of the 1.5v and 2.5v power-on. 1. the 3.3v must be brought up before the1.3v 2. the 1.3v must be brought up before the 1.5v and 2.5v 3. the 1.5v must be brought up before or at the same time as the 0.75v 4. the 2.5v must be brought up before or at the same time as the 1.25v 3.3.2 power-down sequence all the power supplies should be brought down simultaneously. if the user cannot power down all the supplies simultaneously, the power-down sequ ence is recommended to be the reverse order of the power-up sequence shown in section 3.3.1 . gpio[6:5] io cfg_pci_ swin[1:0] select sram bar window size 11?64 mbyte 10?32 mbyte 01?16 mbyte 00? 8 mbyte 2 gpio[7] not used total (per channel) 8 table 29. configuration/gpio pins (sheet 2 of 2) signal name i/o configuration function description number
intel ? IXP2400 network processor datasheet 69 3.3.3 slowport clock behavior during reset in IXP2400 a0 silicon, when the sys_reset_l or the pci_rst_l is asserted, the sp_clk drives out the clock signal at the same frequency as the sys_clk, but 180 degrees out of phase with the sys_clk. after the de-assertion of both sys_reset_l (and pci_rst_l if cfg_rstdir = 1), the sp_clk will drive out the cl ock signal at half of the sys_clk frequency after approximately three sys_clk cycles, or at the programmed frequency. 3.3.4 pullup/pulldown and unused pin guidelines for normal (i.e., non-test mode) operation, terminate signals as follows: typical pullup/pulldown resistor values are in the range of 5-10 kohms. for unused qdr sram channels, the output pins can be left unconnected (no connect). the input pins need to be tied to ground with a 100-kohm resistor. similarly, for unused msf channels, the output pins can be left unconnected (no connect); the input pins need to be tied to ground with a 100-kohm resistor.
intel ? IXP2400 network processor 70 datasheet 3.4 ball information figure 10. IXP2400 network processor ball map (bottom left side) b1456-03 abc def gh j klmnpr t uvw 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 bottom view (left side) abc def gh j klmnpr t uvw d_ ecc[6] d_ ecc[4] d_ dq[25] d_a[4] d_ dq[23] d_dq[1] d_dq[5] d_dq[3] d_dq[2] d_dqs [0] d_dqs [1] d_dqs [3] d_cke [0] d_a[7] d_a[10] d_we_l d_ rcomp [0] d_ rcomp [1] d_ras _l d_cs _l[0] d_ba[0] d_a[9] d_a[6] d_a[11] d_a[3] d_a[0] d_ vref[0] s0_ vref s0_a[23] s0_a[19] s0_a[18] d_ dqs[8] d_ dqs[6] d_ dqs[7] d_ dqs[4] d_ dqs[5] d_ dq[37] d_ dq[32] d_ dq[35] d_ dq[41] d_ dq[36] d_ dq[43] d_ dq[34] d_ dq[19] d_ dq[26] d_ dq[30] d_ dq[44] d_ dq[38] d_ dq[42] d_ dq[48] d_ dq[60] d_ dq[53] d_ dq[51] d_ cs_l[1] d_ dq[46] d_ dq[33] d_ dq[40] d_ dq[55] d_ dq[52] d_ dq[57] d_ dq[49] d_ dq[47] d_ dq[59] d_ dq[58] d_ck[2] d_ck _l[2] d_rcven out_l d_rcv enin_l d_ dq[63] d_ dq[56] d_ dq[61] d_ vref[1] d_ dq[50] d_ dq[62] d_ dq[54] d_ dq[18] d_ dq[21] d_ dq[20] d_ dq[13] d_ dq[14] d_ dq[31] d_ dq[27] d_ dq[11] d_ dq[15] d_ dq[17] s0_ di[12] s0_ di[6] s0_ di[10] s0_ di[15] s0_ cin[1] s0_ cin[0] s0_ cin_l[0] s0_ rpe_l[0] s0_pi[1] s0_di[5] s0_ cin_l[1] s0_di[4] s0_di[1] s0_di[0] s0_pi[0] s0_ do[12] s0_ do[9] s0_ do[4] s0_di[3] s0_a[17] s0_a[22] s0_a[13] s0_a[5] s0_a[16] s0_a[12] s0_a[1] s0_a[0] s0_a[21] s0_c[0] s0_z0[1] s0_z0[0] ther mdc ther mda d_ dqs[2] d_ ecc[5] d_ ecc[0] d_ ecc[1] d_dm[8] d_dm[3] d_dm[5] d_dm[4] d_dm[7] d_dm[6] d_ cas_l d_a[8] d_a[13] d_dm[0] d_dm[2] d_a[12] d_a[5] d_a[1] d_a[2] d_dq[8] d_dq[7] d_dq[6] d_dq[9] d_ dq[24] d_ dq[28] d_dq[0] s0_ di[11] s0_ di[14] d_ck[1] d_dm[1] d_dq[10] d_ba[1] d_ ecc[2] d_ ecc[3] d_ dq[22] s0_a[20] vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc2.5 s0_a[14] vcc1.5 s0_a[15] vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 s0_k[1] s0_k[0] vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 s0_a[10] s0_a[2] s1_a[20] s1_a[12] s1_a[23] s1_a[16] s1_a[7] s1_a[8] s1_a[2] s1_a[9] s1_a[3] s1_a[1] s1_k[1] s1_c[0] s1_c[1] s1_c_l [0] s1_a[21] s1_a[17] s1_a[13] s1_a[22] s1_a[6] s1_a[4] vcc1.5 vcc1.5 s1_a[0] s1_do [15] s0_a[6] s0_a[4] s0_a[3] s0_a[9] s0_di[8] s0_di[9] s0_di[7] s0_a[7] s0_a[8] s0_a[11] vcc1.5 vcc1.5 s0_di[2] vcc1.5 vcc1.5 vcc1.5 vcc1.5 s0_ di[13] vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 s1_ vref vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 s0_bwe _l[0] s0_rpe _l[1] s0_bwe _l[1] s1_bwe _l[0] s1_bwe _l[1] s1_k_l [0] s1_c_l [1] s0_wpe _l[0] s0_wpe _l[1] d_dq[4] d_ dq[29] d_ dq[16] d_ cke[1] vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 txsof [3] vcc3.3 vcc3.3 txeof [3] vcc3.3 txprty [2] txenb [3] txerr [3] txprty [3] vcc2.5 vcc2.5 d_ck[0] d_ck _l[0] vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 vcc2.5 nb nb nb nb nb nb nb nb vcc2.5 vcc2.5 vcc2.5 vcc2.5 d_ ecc[7] s0_po [1] s0_c [1] s0_do [13] s0_do [8] s0_do [10] s0_do [14] s0_do [3] s0_do [6] s0_po [0] s0_do [7] s0_do [2] s0_do [1] s1_di [15] s1_pi [1] s1_di [12] s1_di [13] s1_di [9] s1_di [5] s1_di [2] s1_di [4] s1_a[14] s1_a[15] s1_a[18] s1_a[10] s1_a[19] s1_a[11] s1_a[5] s1_di [10] s1_di [8] s1_di [3] s1_di [1] s1_di [11] s1_di [14] s1_di [6] s1_di [7] s1_di [0] s1_do [3] s1_pi [0] s1_cin [1] s1_cin_ l[0] s1_cin_ l[1] s1_cin_ [0] d_ck_ l[1] d_dq [12] d_dq [39] d_dq [45] s0_do [0] s0_do [11] s0_c _l[0] s0_do [15] s0_do [5] s0_c_l [1] s0_k_l [0] s0_k_l [1] vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc
intel ? IXP2400 network processor datasheet 71 figure 11. IXP2400 network processor ball map (bottom right side) b1459-03 au at ar ap an am al ak aj ah ag af ae ad ac ab aa y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 bottom view (right side) au at ar ap an am al ak aj ah ag af ae ad ac ab aa y txdata [1] txdata [0] txdata [8] txdata [4] txdata [7] txdata [6] txdata [13] txdata [27] txdata [21] txdata [19] rxc data[1] rxc data[0] rxc data[2] rxc data[3] txdata [30] txclk 23 txdata [22] txdata [16] txdata [24] txdata [15] txdata [20] txr comp msf_clk _bypass txdata [23] txdata [17] txdata [25] txdata [18] txdata [14] txaddr [1] rxaddr [3] txdata [11] txdata [9] txdata [12] txdata [10] txdata [5] txeof [1] txsof [1] txcfc txenb [1] txeof [0] txsof [0] txenb [0] txaddr [0] txaddr [2] rxerr [1] rxerr [0] rxprty [1] rxaddr [1] rxpadl [0] txcdata [0] txcdata [1] txcdata [2] rxdata [23] rxenb [0] rxdata [16] rxdata [18] txcpar [0] rxsof [2] rxsof [3] rxeof [3] rxeof [2] rxval [2] rxval [3] rxval [1] rxval [0] txerr [1] txerr [0] rxprty [0] rxprty [2] txprty [0] txprty [1] rxdata [3] rxpadl [1] rxdata [2] rxdata [6] rxdata [0] rxdata [5] rxdata [10] rxdata [1] rxdata [11] rxdata [7] rxdata [14] rxdata [8] rxdata [9] txcdata [3] rxr comp rxdata [12] rxdata [15] rxdata [13] rxdata [4] rxenb [2] pci_rst _l pci_ad [27] pci_ad [18] pci_ serr_l pci_ cbe_l[0] pci_ cbe_l[6] rxsof [0] rxsof [1] txaddr [3] rxenb [1] rxenb [3] rxeof [1] rxclk 01 rxclk 23 rxaddr [2] rxaddr [0] rxdata [21] rxdata [17] rxdata [20] rxdata [27] rxeof [0] txdata [26] txenb [2] txdata [29] txerr [2] txsof [2] vssa vssa vcca vcca sys_ clk vcc3.3 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 vcc1.5 s1_k[0] s1_rpe _l[0] s1_rpe _l[1] s1_wpe _l[0] txdata [31] txeof [2] txdata [28] vcc3.3 rxcsrb txfa[2] txfa[0] rxcpar txclk01 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 txcsof txdata [3] txdata [2] vcc3.3 vcc3.3 rsvd[0] rxfa[1] rsvd[2] rxfa[2] rxfa[3] rsvd[3] txsfa rxcsof vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 vcc3.3 txpadl [0] txpadl [1] rxcfc rsvd[1] txfa[1] txpfa txfa[3] nb nb nb nb nb s1_do [9] s1_zq [1] s1_zq [0] s1_do [12] s1_do [7] s1_do [2] t_diag _clk s1_do [11] s1_do [6] s1_do [0] s1_do [4] s1_do [5] s1_do [8] vcc1.5 gpio[4] gpio[7] gpio[0] gpio[5] vcc1.5 vcc3.3 vcc3.3 t_load vcc3.3 vcc3.3 sp_clk vcc1.5 s1_do [1] pll_ bypass s1_po [0] sp_rd _l s1_do [14] sp_wr _l s1_k_ l[1] sp_cs_ _l[0] serial _tx sp_dir_ sp_a[1] sp_ad [2] sp_ad [1] sp_ad [7] sp_ad [5] tck vcc3.3 trst_l tdo gpio [6] gpio [2] gpio [3] gpio [1] cfg_ rstdir tdi_t_ scan_en sys_ reset _l sys_ reset_ out_l pll_div_ bypass sp_ ale_l sp_cp_ sp_a[0] sp_cs _l[1] sp_ad [6] sp_ad [3] sp_ad [4] pci_ad [39] pci_ad [35] pci_ad [40] pci_ad [45] pci_ad [50] pci_ad [54] pci_ad [55] pci_ad [46] pci_ad [36] pci_ad [59] pci_ req64_l pci_ad [32] pci_ad [37] pci_ad [41] pci_ad [47] pci_ad [51] pci_ad [33] pci_ad [42] pci_ad [52] pci_ad [56] pci_ad [60] pci_ad [0] pci_ad [1] pci_ad [5] pci_ad [9] pci_ad [2] pci_ad [6] pci_ad [11] pci_ad [7] pci_ad [12] pci_ad [15] pci_ad [16] pci_ad [22] pci_ad [17] pci_par pci_ad [23] pci_ad [25] pci_ad [26] pci_ad [31] pci_ad [20] pci_ad [24] pci_ad [29] pci_ad [21] pci_ad [10] pci_ad [30] pci_ad [63] pci_ par64 pci_ ack64_l pci_cbe _l[7] pci_ad [3] pci_ad [4] pci_ad [8] pci_ad [13] pci_ad [19] pci_ad [28] pci_ perr_l pci_ stop_l pci_ trdy_l pci_ devsel _l pci_req _l[1] pci_ intb_l pci_req _l[0] t_sys_ refclk pci_ irdy_l pci_ frame pci_gnt _l[3] pci_gnt _l[0] pci _inta_l pci_ad [14] pci_cbe _l[3] pci_cbe _l[2] pci_cbe _l[1] pci_ad [53] pci_ad [57] pci_ad [61] pci_ad [58] pci_ad [62] pci_ad [38] pci_ rcomp pci_ad [34] pci_ad [43] pci_ad [48] pci_ad [44] pci_ad [49] pci_cbe _l[4] pci_cbe _l[5] pci_ idsel sp_ ack_l sp_oe_l sp_ad [0] serial _rx tms_ t_clk power_ good s1_wpe _l[11] s1_do [10] s1_do [13] s1_po [1] rxfa[0] rxpfa txcsrb rxdata [19] rxdata [24] rxdata [26] rxdata [22] rxdata [25] rxdata [30] rxdata [28] rxdata [31] rxdata [29] rxerr [2] rxprty [3] rxerr [3] pci_clk vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc
IXP2400 network processor 72 datasheet 3.5 ball list tables table 30 defines the signal types on the ball list. ) 3.5.1 balls listed in alphanumeric order by signal name the following ball locations are not associated with a signal, therefore are not listed in table 31 : a1, y1, w1, v1, y37, w37, v37, au[18:20], and a[18:20]. table 31 shows the ball locations and signal names arranged in alphanumeric order by the signal name. table 31. ball list in alphanumeric order by signal location table 30. IXP2400 network processor signal-type abbreviations ball abbreviation electrical description vcc3.3 3.3vdc power 3.3-volt supply for msf, pci and misc. vcc2.5 2.5vdc power 2.5-volt supply for ddr vcc1.5 1.5vdc power 1.5-volt supply for qdr vcc 1.3vdc power 1.3-volt supply for core vss gnd return for 3.3, 2.5, 1.5 and core supplies vcca 1.3vdc pll power supply 1.3 volt vssa see figure 12 for connections. three-state logic high, logic low or high impedance pd pull-down required od open drain pull-up required dnc none do not connect signal name ball location cfg_rstdir ak33 d_a[0] e5 d_a[1] g12 d_a[10] d1 d_a[11] b8 d_a[12] g15 d_a[13] d18 d_a[2] g10 d_a[3] b7 d_a[4] a7 d_a[5] g13 d_a[6] f11 d_a[7] a10 d_a[8] d9 d_a[9] b10 d_ba[0] d4 d_ba[1] b1 d_cas_l k7 d_ck[0] f8 d_ck[1] f18 d_ck[2] n3 d_ck_l[0] g9 d_ck_l[1] g18 d_ck_l[2] n4 d_cke[0] b16 d_cke[1] f15 signal name ball location d_cs_l[0] f2 d_cs_l[1] k1 d_dm[0] c12 d_dm[1] f17 d_dm[2] e13 d_dm[3] d6 d_dm[4] h8 d_dm[5] h4 d_dm[6] k6 d_dm[7] n7 d_dm[8] c5 d_dq[0] c18 d_dq[1] a15 signal name ball location
IXP2400 network processor datasheet 73 d_dq[10] c15 d_dq[11] h16 d_dq[12] g16 d_dq[13] d16 d_dq[14] d13 d_dq[15] h17 d_dq[16] f14 d_dq[17] c11 d_dq[18] d10 d_dq[19] c8 d_dq[2] b14 d_dq[20] d15 d_dq[21] d12 d_dq[22] b11 d_dq[23] a9 d_dq[24] e11 d_dq[25] a6 d_dq[26] d7 d_dq[27] h14 d_dq[28] e10 d_dq[29] f12 d_dq[3] b17 d_dq[30] e7 d_dq[31] h13 d_dq[32] d3 d_dq[33] e4 d_dq[34] f6 d_dq[35] f3 d_dq[36] f5 d_dq[37] c3 d_dq[38] j9 d_dq[39] g7 d_dq[4] a13 d_dq[40] g4 d_dq[41] g3 d_dq[42] j8 d_dq[43] h5 d_dq[44] h7 signal name ball location d_dq[45] g6 d_dq[46] j2 d_dq[47] l2 d_dq[48] j6 d_dq[49] l7 d_dq[5] a16 d_dq[50] l5 d_dq[51] j3 d_dq[52] l8 d_dq[53] j5 d_dq[54] l4 d_dq[55] k4 d_dq[56] l1 d_dq[57] m8 d_dq[58] m3 d_dq[59] m2 d_dq[6] e17 d_dq[60] n6 d_dq[61] n1 d_dq[62] m5 d_dq[63] p2 d_dq[7] c17 d_dq[8] c14 d_dq[9] e16 d_dqs[0] b13 d_dqs[1] e14 d_dqs[2] c9 d_dqs[3] e8 d_dqs[4] c2 d_dqs[5] h2 d_dqs[6] k3 d_dqs[7] m6 d_dqs[8] b4 d_ecc[0] h10 d_ecc[1] h11 d_ecc[2] b5 d_ecc[3] b2 d_ecc[4] c6 signal name ball location d_ecc[5] f9 d_ecc[6] a4 d_ecc[7] a3 d_ras_l e2 d_rcomp[0] g1 d_rcomp[1] h1 d_rcvenin_l p5 d_rcvenout_l p4 d_vref[0] a12 d_vref[1] p1 d_we_l e1 gpio[0] af31 gpio[1] ak34 gpio[2] aj33 gpio[3] aj34 gpio[4] ae30 gpio[5] af33 gpio[6] ag34 gpio[7] af30 msf_clk_bypass ac3 pci_ack64_l ap30 pci_ad[0] ap29 pci_ad[1] ar29 pci_ad[10] ar27 pci_ad[11] at27 pci_ad[12] au27 pci_ad[13] am26 pci_ad[14] an26 pci_ad[15] ap26 pci_ad[16] at24 pci_ad[17] au24 pci_ad[18] al23 pci_ad[19] am23 pci_ad[2] at29 pci_ad[20] ap23 pci_ad[21] ar23 pci_ad[22] at23 pci_ad[23] au23 signal name ball location
IXP2400 network processor 74 datasheet pci_ad[24] ap22 pci_ad[25] at22 pci_ad[26] au22 pci_ad[27] al21 pci_ad[28] am21 pci_ad[29] ap21 pci_ad[3] am28 pci_ad[30] ar21 pci_ad[31] at21 pci_ad[32] ap37 pci_ad[33] ar37 pci_ad[34] at37 pci_ad[35] am36 pci_ad[36] an36 pci_ad[37] ap36 pci_ad[38] at36 pci_ad[39] am37 pci_ad[4] an28 pci_ad[40] am35 pci_ad[41] ap35 pci_ad[42] ar35 pci_ad[43] at35 pci_ad[44] au35 pci_ad[45] am34 pci_ad[46] an34 pci_ad[47] ap34 pci_ad[48] at34 pci_ad[49] au34 pci_ad[5] ap28 pci_ad[50] am33 pci_ad[51] ap33 pci_ad[52] ar33 pci_ad[53] at33 pci_ad[54] am32 pci_ad[55] an32 pci_ad[56] ap32 pci_ad[57] at32 pci_ad[58] au32 signal name ball location pci_ad[59] am31 pci_ad[6] at28 pci_ad[60] ap31 pci_ad[61] at31 pci_ad[62] au31 pci_ad[63] am30 pci_ad[7] au28 pci_ad[8] am27 pci_ad[9] ap27 pci_cbe_l[0] al27 pci_cbe_l[1] at26 pci_cbe_l[2] ap24 pci_cbe_l[3] an22 pci_cbe_l[4] at30 pci_cbe_l[5] au30 pci_cbe_l[6] al29 pci_cbe_l[7] am29 pci_clk at19 pci_devsel_l ar25 pci_frame_l an24 pci_gnt_l[0] ar20 pci_gnt_l[1] an20 pci_idsel am22 pci_inta_l ap20 pci_intb_l am19 pci_irdy_l am24 pci_par au26 pci_par64 an30 pci_perr_l am25 pci_rcomp au36 pci_req_l[0] ap19 pci_req_l[1] am20 pci_req64_l ar31 pci_rst_l al19 pci_serr_l al25 pci_stop_l ap25 pci_trdy_l at25 pll_bypass aj31 signal name ball location pll_div_bypass ah35 rsvd[0] aj6 rsvd[1] af2 rsvd[2] an12 rsvd[3] am9 rxaddr[0] ap10 rxaddr[1] al11 rxaddr[2] an10 rxaddr[3] am10 rxcdata[0] ae4 rxcdata[1] ad3 rxcdata[2] ad5 rxcdata[3] ad6 rxcfc af7 rxclk01 ap8 rxclk23 ap9 rxcpar ad7 rxcsof ae2 rxcsrb ad1 rxdata[0] at3 rxdata[1] ap6 rxdata[10] ap5 rxdata[11] ap7 rxdata[12] at7 rxdata[13] ar5 rxdata[14] au4 rxdata[15] at8 rxdata[16] am14 rxdata[17] ap13 rxdata[18] an14 rxdata[19] at10 rxdata[2] ap3 rxdata[20] ar13 rxdata[21] ap12 rxdata[22] at12 rxdata[23] ar11 rxdata[24] au10 rxdata[25] at13 signal name ball location
IXP2400 network processor datasheet 75 rxdata[26] at11 rxdata[27] ap14 rxdata[28] au12 rxdata[29] at15 rxdata[3] ap2 rxdata[30] at14 rxdata[31] au14 rxdata[4] ar7 rxdata[5] ap4 rxdata[6] ar3 rxdata[7] at4 rxdata[8] at5 rxdata[9] at6 rxenb[0] ap11 rxenb[1] an8 rxenb[2] am15 rxenb[3] ar9 rxeof[0] al1 rxeof[1] ar1 rxeof[2] ap16 rxeof[3] ar17 rxerr[0] am5 rxerr[1] al7 rxerr[2] at16 rxerr[3] at17 rxfa[0] at1 rxfa[1] an6 rxfa[2] an16 rxfa[3] ar15 rxpadl[0] am8 rxpadl[1] au2 rxpfa at2 rxprty[0] ap1 rxprty[1] al9 rxprty[2] ap17 rxprty[3] au16 rxrcomp au8 rxsof[0] al5 signal name ball location rxsof[1] an4 rxsof[2] al17 rxsof[3] am17 rxval[0] am4 rxval[1] am6 rxval[2] am16 rxval[3] ap15 s0_a[0] e27 s0_a[1] c27 s0_a[10] e25 s0_a[11] f24 s0_a[12] c26 s0_a[13] d28 s0_a[14] b27 s0_a[15] b29 s0_a[16] c28 s0_a[17] c25 s0_a[18] a30 s0_a[19] a28 s0_a[2] h25 s0_a[20] b25 s0_a[21] c29 s0_a[22] d24 s0_a[23] a26 s0_a[3] g26 s0_a[4] f26 s0_a[5] d26 s0_a[6] f25 s0_a[7] f27 s0_a[8] f28 s0_a[9] g24 s0_bwe_l[0] b33 s0_bwe_l[1] h27 s0_c[0] f29 s0_c[1] a34 s0_c_l[0] e29 s0_c_l[1] a32 s0_cin[0] e21 signal name ball location s0_cin[1] c22 s0_cin_l[0] d20 s0_cin_l[1] f20 s0_di[0] h23 s0_di[1] f23 s0_di[10] b21 s0_di[11] f19 s0_di[12] c19 s0_di[13] e19 s0_di[14] h19 s0_di[15] b23 s0_di[2] e23 s0_di[3] c24 s0_di[4] f22 s0_di[5] d22 s0_di[6] c21 s0_di[7] g22 s0_di[8] g20 s0_di[9] c20 s0_do[0] g28 s0_do[1] g31 s0_do[10] e35 s0_do[11] f30 s0_do[12] d32 s0_do[13] b35 s0_do[14] e31 s0_do[15] e33 s0_do[2] g33 s0_do[3] f32 s0_do[4] d36 s0_do[5] c36 s0_do[6] f34 s0_do[7] g35 s0_do[8] c35 s0_do[9] d34 s0_k[0] c31 s0_k[1] b31 s0_k_l[0] c30 signal name ball location
IXP2400 network processor 76 datasheet s0_k_l[1] c32 s0_pi[0] f21 s0_pi[1] c23 s0_po[0] f36 s0_po[1] a36 s0_rpe_l[0] d30 s0_rpe_l[1] c33 s0_vref a24 s0_wpe_l[0] c34 s0_wpe_l[1] c37 s0_zq[0] j30 s0_zq[1] h29 s1_a[0] u36 s1_a[1] t35 s1_a[10] r35 s1_a[11] r36 s1_a[12] r30 s1_a[13] r32 s1_a[14] p34 s1_a[15] p35 s1_a[16] p31 s1_a[17] p32 s1_a[18] n35 s1_a[19] n36 s1_a[2] v32 s1_a[20] n30 s1_a[21] n32 s1_a[22] n33 s1_a[23] m31 s1_a[3] v34 s1_a[4] u33 s1_a[5] t37 s1_a[6] r33 s1_a[7] t31 s1_a[8] t32 s1_a[9] t34 s1_bwe_l[0] u30 s1_bwe_l[1] w32 signal name ball location s1_c[0] w35 s1_c[1] w36 s1_c_l[0] v31 s1_c_l[1] u35 s1_cin[0] l33 s1_cin[1] k35 s1_cin_l[0] j36 s1_cin_l[1] l35 s1_di[0] m32 s1_di[1] p37 s1_di[10] h35 s1_di[11] j33 s1_di[12] h30 s1_di[13] h32 s1_di[14] j32 s1_di[15] k31 s1_di[2] m34 s1_di[3] k37 s1_di[4] m35 s1_di[5] k34 s1_di[6] k32 s1_di[7] l32 s1_di[8] j35 s1_di[9] h34 s1_do[0] ab32 s1_do[1] ad31 s1_do[10] aa33 s1_do[11] ac33 s1_do[12] y32 s1_do[13] y34 s1_do[14] ad34 s1_do[15] w33 s1_do[2] ac30 s1_do[3] w30 s1_do[4] ab34 s1_do[5] ab35 s1_do[6] ac32 s1_do[7] aa32 signal name ball location s1_do[8] ab37 s1_do[9] y31 s1_k[0] ac35 s1_k[1] v35 s1_k_l[0] u32 s1_k_l[1] ad35 s1_pi[0] l30 s1_pi[1] l36 s1_po[0] ad32 s1_po[1] y35 s1_rpe_l[0] aa35 s1_rpe_l[1] aa36 s1_vref e37 s1_wpe_l[0] ac36 s1_wpe_l[1] ad37 s1_zq[0] aa30 s1_zq[1] ab31 serial_rx ag32 serial_tx af35 sp_ack_l ak36 sp_ad[0] aj36 sp_ad[1] af36 sp_ad[2] ae36 sp_ad[3] aj37 sp_ad[4] ak37 sp_ad[5] af32 sp_ad[6] ag37 sp_ad[7] af37 sp_ale_l aj35 sp_clk al36 sp_cp_sp_a[0] al35 sp_cs_l[0] ae35 sp_cs_l[1] ag36 sp_dir_sp_a[1] ae33 sp_oe_l ak35 sp_rd_l ae32 sp_wr_l af34 sys_clk ar18 signal name ball location
IXP2400 network processor datasheet 77 sys_reset_l ag35 sys_reset_out_l ah36 t_diag_clk ah30 t_load ak32 t_sys_refclk am18 tck ag30 tdi_t_scan_en al33 tdo ag33 thermda j18 thermdc j19 tms_t_clk aj32 trst_l ag31 tst_reset_l al32 txaddr[0] ak2 txaddr[1] aj8 txaddr[2] ak1 txaddr[3] al3 txcdata[0] al13 txcdata[1] am13 txcdata[2] am11 txcdata[3] au6 txcfc am7 txclk01 ad8 txclk23 ab2 txcpar al15 txcsof am12 txcsrb at9 txdata[0] ah7 txdata[1] ah8 txdata[10] ag1 txdata[11] ag7 txdata[12] ag3 txdata[13] ah2 txdata[14] af8 txdata[15] af5 txdata[16] ab4 txdata[17] ab6 txdata[18] ab8 signal name ball location txdata[19] ad2 txdata[2] aj2 txdata[20] ac5 txdata[21] aa2 txdata[22] aa4 txdata[23] aa6 txdata[24] ab5 txdata[25] ab7 txdata[26] aa8 txdata[27] y2 txdata[28] y4 txdata[29] ab3 txdata[3] aj4 txdata[30] ab1 txdata[31] y6 txdata[4] ah5 txdata[5] ah1 txdata[6] ah3 txdata[7] ah4 txdata[8] ah6 txdata[9] ag5 txenb[0] ak3 txenb[1] ak6 txenb[2] y3 txenb[3] v4 txeof[0] ak5 txeof[1] ak8 txeof[2] y8 txeof[3] w7 txerr[0] am1 txerr[1] am3 txerr[2] y5 txerr[3] v6 txfa[0] ae8 txfa[1] af3 txfa[2] ad4 txfa[3] ac7 txpadl[0] af4 signal name ball location txpadl[1] af6 txpfa af1 txprty[0] am2 txprty[1] an2 txprty[2] w3 txprty[3] v2 txrcomp ac1 txsfa ae6 txsof[0] ak4 txsof[1] ak7 txsof[2] y7 txsof[3] w5 vcc aj29 vcc ag29 vcc ae29 vcc ac29 vcc aa29 vcc w29 vcc u29 vcc r29 vcc n29 vcc l29 vcc j29 vcc ak28 vcc ah28 vcc af28 vcc ad28 vcc ab28 vcc y28 vcc v28 vcc t28 vcc p28 vcc m28 vcc k28 vcc aj27 vcc ag27 vcc ae27 vcc ac27 signal name ball location
IXP2400 network processor 78 datasheet vcc aa27 vcc w27 vcc u27 vcc r27 vcc n27 vcc l27 vcc j27 vcc ak26 vcc ah26 vcc af26 vcc ad26 vcc ab26 vcc y26 vcc v26 vcc t26 vcc p26 vcc m26 vcc k26 vcc aj25 vcc ag25 vcc ae25 vcc ac25 vcc aa25 vcc w25 vcc u25 vcc r25 vcc n25 vcc l25 vcc j25 vcc ak24 vcc ah24 vcc af24 vcc ad24 vcc ab24 vcc y24 vcc v24 vcc t24 vcc p24 signal name ball location vcc m24 vcc k24 vcc aj23 vcc ag23 vcc ae23 vcc ac23 vcc aa23 vcc w23 vcc u23 vcc r23 vcc n23 vcc l23 vcc j23 vcc ak22 vcc ah22 vcc af22 vcc ad22 vcc ab22 vcc y22 vcc v22 vcc t22 vcc p22 vcc m22 vcc k22 vcc aj21 vcc ag21 vcc ae21 vcc ac21 vcc aa21 vcc w21 vcc u21 vcc r21 vcc n21 vcc l21 vcc j21 vcc ak20 vcc ah20 vcc af20 signal name ball location vcc ad20 vcc ab20 vcc y20 vcc v20 vcc t20 vcc p20 vcc m20 vcc k20 vcc aj19 vcc ag19 vcc ae19 vcc ac19 vcc aa19 vcc w19 vcc u19 vcc r19 vcc n19 vcc l19 vcc ak18 vcc ah18 vcc af18 vcc ad18 vcc ab18 vcc y18 vcc v18 vcc t18 vcc p18 vcc m18 vcc k18 vcc aj17 vcc ag17 vcc ae17 vcc ac17 vcc aa17 vcc w17 vcc u17 vcc r17 vcc n17 signal name ball location
IXP2400 network processor datasheet 79 vcc l17 vcc j17 vcc ak16 vcc ah16 vcc af16 vcc ad16 vcc ab16 vcc y16 vcc v16 vcc t16 vcc p16 vcc m16 vcc k16 vcc aj15 vcc ag15 vcc ae15 vcc ac15 vcc aa15 vcc w15 vcc u15 vcc r15 vcc n15 vcc l15 vcc j15 vcc ak14 vcc ah14 vcc af14 vcc ad14 vcc ab14 vcc y14 vcc v14 vcc t14 vcc p14 vcc m14 vcc k14 vcc aj13 vcc ag13 vcc ae13 signal name ball location vcc ac13 vcc aa13 vcc w13 vcc u13 vcc r13 vcc n13 vcc l13 vcc j13 vcc ak12 vcc ah12 vcc af12 vcc ad12 vcc ab12 vcc y12 vcc v12 vcc t12 vcc p12 vcc m12 vcc k12 vcc aj11 vcc ag11 vcc ae11 vcc ac11 vcc aa11 vcc w11 vcc u11 vcc r11 vcc n11 vcc l11 vcc j11 vcc ak10 vcc ah10 vcc af10 vcc ad10 vcc ab10 vcc y10 vcc v10 vcc t10 signal name ball location vcc p10 vcc m10 vcc k10 vcc aj9 vcc ag9 vcc ae9 vcc ac9 vcc aa9 vcc w9 vcc u9 vcc r9 vcc n9 vcc l9 vcc1.5 ad36 vcc1.5 ab36 vcc1.5 y36 vcc1.5 v36 vcc1.5 t36 vcc1.5 p36 vcc1.5 m36 vcc1.5 k36 vcc1.5 g36 vcc1.5 e36 vcc1.5 b36 vcc1.5 e34 vcc1.5 b34 vcc1.5 ad33 vcc1.5 ab33 vcc1.5 y33 vcc1.5 v33 vcc1.5 t33 vcc1.5 p33 vcc1.5 m33 vcc1.5 k33 vcc1.5 h33 vcc1.5 f33 vcc1.5 e32 vcc1.5 b32 signal name ball location
IXP2400 network processor 80 datasheet vcc1.5 h31 vcc1.5 ad30 vcc1.5 ab30 vcc1.5 y30 vcc1.5 v30 vcc1.5 t30 vcc1.5 p30 vcc1.5 m30 vcc1.5 k30 vcc1.5 g30 vcc1.5 e30 vcc1.5 b30 vcc1.5 h28 vcc1.5 e28 vcc1.5 b28 vcc1.5 h26 vcc1.5 e26 vcc1.5 b26 vcc1.5 h24 vcc1.5 e24 vcc1.5 b24 vcc1.5 h22 vcc1.5 e22 vcc1.5 b22 vcc1.5 h20 vcc1.5 e20 vcc1.5 b20 vcc2.5 h18 vcc2.5 e18 vcc2.5 b18 vcc2.5 f16 vcc2.5 c16 vcc2.5 g14 vcc2.5 d14 vcc2.5 a14 vcc2.5 h12 vcc2.5 e12 vcc2.5 b12 signal name ball location vcc2.5 f10 vcc2.5 c10 vcc2.5 n8 vcc2.5 k8 vcc2.5 g8 vcc2.5 d8 vcc2.5 a8 vcc2.5 p6 vcc2.5 l6 vcc2.5 h6 vcc2.5 e6 vcc2.5 b6 vcc2.5 r4 vcc2.5 m4 vcc2.5 j4 vcc2.5 f4 vcc2.5 c4 vcc2.5 r2 vcc2.5 n2 vcc2.5 k2 vcc2.5 g2 vcc2.5 d2 vcc2.5 a2 vcc3.3 au37 vcc3.3 an37 vcc3.3 an35 vcc3.3 al34 vcc3.3 ah34 vcc3.3 ae34 vcc3.3 au33 vcc3.3 an33 vcc3.3 ah32 vcc3.3 an31 vcc3.3 al30 vcc3.3 aj30 vcc3.3 au29 vcc3.3 an29 vcc3.3 an27 signal name ball location vcc3.3 au25 vcc3.3 an25 vcc3.3 an23 vcc3.3 au21 vcc3.3 an21 vcc3.3 an19 vcc3.3 au17 vcc3.3 an17 vcc3.3 au15 vcc3.3 an15 vcc3.3 au13 vcc3.3 an13 vcc3.3 au11 vcc3.3 an11 vcc3.3 au9 vcc3.3 an9 vcc3.3 au7 vcc3.3 an7 vcc3.3 aj7 vcc3.3 ae7 vcc3.3 aa7 vcc3.3 v7 vcc3.3 au5 vcc3.3 an5 vcc3.3 aj5 vcc3.3 ae5 vcc3.3 aa5 vcc3.3 v5 vcc3.3 au3 vcc3.3 an3 vcc3.3 aj3 vcc3.3 ae3 vcc3.3 aa3 vcc3.3 v3 vcc3.3 au1 vcc3.3 an1 vcc3.3 aj1 vcc3.3 ae1 signal name ball location
IXP2400 network processor datasheet 81 vcc3.3 aa1 vcca ap18 vcca an18 vss al37 vss ah37 vss ae37 vss ac37 vss aa37 vss u37 vss r37 vss n37 vss m37 vss l37 vss j37 vss h37 vss g37 vss f37 vss d37 vss b37 vss a37 vss ar36 vss h36 vss f35 vss d35 vss a35 vss ar34 vss ac34 vss aa34 vss w34 vss u34 vss r34 vss n34 vss l34 vss j34 vss g34 vss ah33 vss d33 vss a33 signal name ball location vss ar32 vss g32 vss al31 vss ak31 vss ah31 vss ae31 vss ac31 vss aa31 vss w31 vss u31 vss r31 vss n31 vss l31 vss j31 vss f31 vss d31 vss a31 vss ar30 vss ak30 vss ak29 vss ah29 vss af29 vss ad29 vss ab29 vss y29 vss v29 vss t29 vss p29 vss m29 vss k29 vss g29 vss d29 vss a29 vss ar28 vss al28 vss aj28 vss ag28 vss ae28 signal name ball location vss ac28 vss aa28 vss w28 vss u28 vss r28 vss n28 vss l28 vss j28 vss ak27 vss ah27 vss af27 vss ad27 vss ab27 vss y27 vss v27 vss t27 vss p27 vss m27 vss k27 vss g27 vss d27 vss a27 vss ar26 vss al26 vss aj26 vss ag26 vss ae26 vss ac26 vss aa26 vss w26 vss u26 vss r26 vss n26 vss l26 vss j26 vss ak25 vss ah25 vss af25 signal name ball location
IXP2400 network processor 82 datasheet vss ad25 vss ab25 vss y25 vss v25 vss t25 vss p25 vss m25 vss k25 vss g25 vss d25 vss a25 vss ar24 vss al24 vss aj24 vss ag24 vss ae24 vss ac24 vss aa24 vss w24 vss u24 vss r24 vss n24 vss l24 vss j24 vss ak23 vss ah23 vss af23 vss ad23 vss ab23 vss y23 vss v23 vss t23 vss p23 vss m23 vss k23 vss g23 vss d23 vss a23 signal name ball location vss ar22 vss al22 vss aj22 vss ag22 vss ae22 vss ac22 vss aa22 vss w22 vss u22 vss r22 vss n22 vss l22 vss j22 vss a22 vss ak21 vss ah21 vss af21 vss ad21 vss ab21 vss y21 vss v21 vss t21 vss p21 vss m21 vss k21 vss h21 vss g21 vss d21 vss a21 vss at20 vss al20 vss aj20 vss ag20 vss ae20 vss ac20 vss aa20 vss w20 vss u20 signal name ball location vss r20 vss n20 vss l20 vss j20 vss ar19 vss ak19 vss ah19 vss af19 vss ad19 vss ab19 vss y19 vss v19 vss t19 vss p19 vss m19 vss k19 vss g19 vss d19 vss b19 vss aj18 vss ag18 vss ae18 vss ac18 vss aa18 vss w18 vss u18 vss r18 vss n18 vss l18 vss ak17 vss ah17 vss af17 vss ad17 vss ab17 vss y17 vss v17 vss t17 vss p17 signal name ball location
IXP2400 network processor datasheet 83 vss m17 vss k17 vss g17 vss d17 vss a17 vss ar16 vss al16 vss aj16 vss ag16 vss ae16 vss ac16 vss aa16 vss w16 vss u16 vss r16 vss n16 vss l16 vss j16 vss ak15 vss ah15 vss af15 vss ad15 vss ab15 vss y15 vss v15 vss t15 vss p15 vss m15 vss k15 vss h15 vss e15 vss b15 vss ar14 vss al14 vss aj14 vss ag14 vss ae14 vss ac14 signal name ball location vss aa14 vss w14 vss u14 vss r14 vss n14 vss l14 vss j14 vss ak13 vss ah13 vss af13 vss ad13 vss ab13 vss y13 vss v13 vss t13 vss p13 vss m13 vss k13 vss f13 vss c13 vss ar12 vss al12 vss aj12 vss ag12 vss ae12 vss ac12 vss aa12 vss w12 vss u12 vss r12 vss n12 vss l12 vss j12 vss ak11 vss ah11 vss af11 vss ad11 vss ab11 signal name ball location vss y11 vss v11 vss t11 vss p11 vss m11 vss k11 vss g11 vss d11 vss a11 vss ar10 vss al10 vss aj10 vss ag10 vss ae10 vss ac10 vss aa10 vss w10 vss u10 vss r10 vss n10 vss l10 vss j10 vss ak9 vss ah9 vss af9 vss ad9 vss ab9 vss y9 vss v9 vss t9 vss p9 vss m9 vss k9 vss h9 vss e9 vss b9 vss ar8 vss al8 signal name ball location
IXP2400 network processor 84 datasheet vss ag8 vss ac8 vss w8 vss v8 vss u8 vss t8 vss r8 vss p8 vss u7 vss t7 vss r7 vss p7 vss m7 vss j7 vss f7 vss c7 vss ar6 vss al6 vss ag6 vss ac6 vss w6 vss u6 vss t6 vss r6 vss u5 vss t5 vss r5 vss n5 vss k5 vss g5 vss d5 vss a5 vss ar4 vss al4 vss ag4 vss ac4 vss w4 vss u4 signal name ball location vss t4 vss u3 vss t3 vss r3 vss p3 vss l3 vss h3 vss e3 vss b3 vss ar2 vss al2 vss ag2 vss ac2 vss w2 vss u2 vss t2 vss u1 vss t1 vss r1 vss m1 vss j1 vss f1 vss c1 vssa at18 vssa al18 signal name ball location
IXP2400 network processor datasheet 85 3.5.2 balls listed in alphanumeric order by ball location the following ball locations are not associated with a signal, therefore are not listed in table 32 : a1, y1, w1, v1, y37, w37, v37, au[18:20], and a[18:20]. table 32 shows the ball locations and signal names arranged in alphanumeric order by ball location. table 32. ball list in alphanumeric order by ball location ball location signal name a2 vcc2.5 a3 d_ecc[7] a4 d_ecc[6] a5 vss a6 d_dq[25] a7 d_a[4] a8 vcc2.5 a9 d_dq[23] a10 d_a[7] a11 vss a12 d_vref[0] a13 d_dq[4] a14 vcc2.5 a15 d_dq[1] a16 d_dq[5] a17 vss a21 vss a22 vss a23 vss a24 s0_vref a25 vss a26 s0_a[23] a27 vss a28 s0_a[19] a29 vss a30 s0_a[18] a31 vss a32 s0_c_l[1] a33 vss a34 s0_c[1] a35 vss a36 s0_po[1] a37 vss aa1 vcc3.3 aa2 txdata[21] aa3 vcc3.3 aa4 txdata[22] aa5 vcc3.3 aa6 txdata[23] aa7 vcc3.3 aa8 txdata[26] aa9 vcc aa10 vss aa11 vcc aa12 vss aa13 vcc aa14 vss aa15 vcc aa16 vss aa17 vcc aa18 vss aa19 vcc aa20 vss aa21 vcc aa22 vss aa23 vcc aa24 vss aa25 vcc aa26 vss aa27 vcc aa28 vss aa29 vcc ball location signal name aa30 s1_zq[0] aa31 vss aa32 s1_do[7] aa33 s1_do[10] aa34 vss aa35 s1_rpe_l[0] aa36 s1_rpe_l[1] aa37 vss ab1 txdata[30] ab2 txclk23 ab3 txdata[29] ab4 txdata[16] ab5 txdata[24] ab6 txdata[17] ab7 txdata[25] ab8 txdata[18] ab9 vss ab10 vcc ab11 vss ab12 vcc ab13 vss ab14 vcc ab15 vss ab16 vcc ab17 vss ab18 vcc ab19 vss ab20 vcc ab21 vss ab22 vcc ab23 vss ball location signal name
IXP2400 network processor 86 datasheet ab24 vcc ab25 vss ab26 vcc ab27 vss ab28 vcc ab29 vss ab30 vcc1.5 ab31 s1_zq[1] ab32 s1_do[0] ab33 vcc1.5 ab34 s1_do[4] ab35 s1_do[5] ab36 vcc1.5 ab37 s1_do[8] ac1 txrcomp ac2 vss ac3 msf_clk_bypass ac4 vss ac5 txdata[20] ac6 vss ac7 txfa[3] ac8 vss ac9 vcc ac10 vss ac11 vcc ac12 vss ac13 vcc ac14 vss ac15 vcc ac16 vss ac17 vcc ac18 vss ac19 vcc ac20 vss ac21 vcc ac22 vss ac23 vcc ac24 vss ball location signal name ac25 vcc ac26 vss ac27 vcc ac28 vss ac29 vcc ac30 s1_do[2] ac31 vss ac32 s1_do[6] ac33 s1_do[11] ac34 vss ac35 s1_k[0] ac36 s1_wpe_l[0] ac37 vss ad1 rxcsrb ad2 txdata[19] ad3 rxcdata[1] ad4 txfa[2] ad5 rxcdata[2] ad6 rxcdata[3] ad7 rxcpar ad8 txclk01 ad9 vss ad10 vcc ad11 vss ad12 vcc ad13 vss ad14 vcc ad15 vss ad16 vcc ad17 vss ad18 vcc ad19 vss ad20 vcc ad21 vss ad22 vcc ad23 vss ad24 vcc ad25 vss ball location signal name ad26 vcc ad27 vss ad28 vcc ad29 vss ad30 vcc1.5 ad31 s1_do[1] ad32 s1_po[0] ad33 vcc1.5 ad34 s1_do[14] ad35 s1_k_l[1] ad36 vcc1.5 ad37 s1_wpe_l[1] ae1 vcc3.3 ae2 rxcsof ae3 vcc3.3 ae4 rxcdata[0] ae5 vcc3.3 ae6 txsfa ae7 vcc3.3 ae8 txfa[0] ae9 vcc ae10 vss ae11 vcc ae12 vss ae13 vcc ae14 vss ae15 vcc ae16 vss ae17 vcc ae18 vss ae19 vcc ae20 vss ae21 vcc ae22 vss ae23 vcc ae24 vss ae25 vcc ae26 vss ball location signal name
IXP2400 network processor datasheet 87 ae27 vcc ae28 vss ae29 vcc ae30 gpio[4] ae31 vss ae32 sp_rd_l ae33 sp_dir_sp_a[1] ae34 vcc3.3 ae35 sp_cs_l[0] ae36 sp_ad[2] ae37 vss af1 txpfa af2 rsvd[1] af3 txfa[1] af4 txpadl[0] af5 txdata[15] af6 txpadl[1] af7 rxcfc af8 txdata[14] af9 vss af10 vcc af11 vss af12 vcc af13 vss af14 vcc af15 vss af16 vcc af17 vss af18 vcc af19 vss af20 vcc af21 vss af22 vcc af23 vss af24 vcc af25 vss af26 vcc af27 vss ball location signal name af28 vcc af29 vss af30 gpio[7] af31 gpio[0] af32 sp_ad[5] af33 gpio[5] af34 sp_wr_l af35 serial_tx af36 sp_ad[1] af37 sp_ad[7] ag1 txdata[10] ag2 vss ag3 txdata[12] ag4 vss ag5 txdata[9] ag6 vss ag7 txdata[11] ag8 vss ag9 vcc ag10 vss ag11 vcc ag12 vss ag13 vcc ag14 vss ag15 vcc ag16 vss ag17 vcc ag18 vss ag19 vcc ag20 vss ag21 vcc ag22 vss ag23 vcc ag24 vss ag25 vcc ag26 vss ag27 vcc ag28 vss ball location signal name ag29 vcc ag30 tck ag31 trst_l ag32 serial_rx ag33 tdo ag34 gpio[6] ag35 sys_reset_l ag36 sp_cs_l[1] ag37 sp_ad[6] ah1 txdata[5] ah2 txdata[13] ah3 txdata[6] ah4 txdata[7] ah5 txdata[4] ah6 txdata[8] ah7 txdata[0] ah8 txdata[1] ah9 vss ah10 vcc ah11 vss ah12 vcc ah13 vss ah14 vcc ah15 vss ah16 vcc ah17 vss ah18 vcc ah19 vss ah20 vcc ah21 vss ah22 vcc ah23 vss ah24 vcc ah25 vss ah26 vcc ah27 vss ah28 vcc ah29 vss ball location signal name
IXP2400 network processor 88 datasheet ah30 t_diag_clk ah31 vss ah32 vcc3.3 ah33 vss ah34 vcc3.3 ah35 pll_div_bypass ah36 sys_reset_out_l ah37 vss aj1 vcc3.3 aj2 txdata[2] aj3 vcc3.3 aj4 txdata[3] aj5 vcc3.3 aj6 rsvd[0] aj7 vcc3.3 aj8 txaddr[1] aj9 vcc aj10 vss aj11 vcc aj12 vss aj13 vcc aj14 vss aj15 vcc aj16 vss aj17 vcc aj18 vss aj19 vcc aj20 vss aj21 vcc aj22 vss aj23 vcc aj24 vss aj25 vcc aj26 vss aj27 vcc aj28 vss aj29 vcc aj30 vcc3.3 ball location signal name aj31 pll_bypass aj32 tms_t_clk aj33 gpio[2] aj34 gpio[3] aj35 sp_ale_l aj36 sp_ad[0] aj37 sp_ad[3] ak1 txaddr[2] ak2 txaddr[0] ak3 txenb[0] ak4 txsof[0] ak5 txeof[0] ak6 txenb[1] ak7 txsof[1] ak8 txeof[1] ak9 vss ak10 vcc ak11 vss ak12 vcc ak13 vss ak14 vcc ak15 vss ak16 vcc ak17 vss ak18 vcc ak19 vss ak20 vcc ak21 vss ak22 vcc ak23 vss ak24 vcc ak25 vss ak26 vcc ak27 vss ak28 vcc ak29 vss ak30 vss ak31 vss ball location signal name ak32 t_load ak33 cfg_rstdir ak34 gpio[1] ak35 sp_oe_l ak36 sp_ack_l ak37 sp_ad[4] al1 rxeof[0] al2 vss al3 txaddr[3] al4 vss al5 rxsof[0] al6 vss al7 rxerr[1] al8 vss al9 rxprty[1] al10 vss al11 rxaddr[1] al12 vss al13 txcdata[0] al14 vss al15 txcpar al16 vss al17 rxsof[2] al18 vssa al19 pci_rst_l al20 vss al21 pci_ad[27] al22 vss al23 pci_ad[18] al24 vss al25 pci_serr_l al26 vss al27 pci_cbe_l[0] al28 vss al29 pci_cbe_l[6] al30 vcc3.3 al31 vss al32 tst_reset_l ball location signal name
IXP2400 network processor datasheet 89 al33 tdi_t_scan_en al34 vcc3.3 al35 sp_cp_sp_a[0] al36 sp_clk al37 vss am1 txerr[0] am2 txprty[0] am3 txerr[1] am4 rxval[0] am5 rxerr[0] am6 rxval[1] am7 txcfc am8 rxpadl[0] am9 rsvd[3] am10 rxaddr[3] am11 txcdata[2] am12 txcsof am13 txcdata[1] am14 rxdata[16] am15 rxenb[2] am16 rxval[2] am17 rxsof[3] am18 t_sys_refclk am19 pci_intb_l am20 pci_req_l[1] am21 pci_ad[28] am22 pci_idsel am23 pci_ad[19] am24 pci_irdy_l am25 pci_perr_l am26 pci_ad[13] am27 pci_ad[8] am28 pci_ad[3] am29 pci_cbe_l[7] am30 pci_ad[63] am31 pci_ad[59] am32 pci_ad[54] am33 pci_ad[50] ball location signal name am34 pci_ad[45] am35 pci_ad[40] am36 pci_ad[35] am37 pci_ad[39] an1 vcc3.3 an2 txprty[1] an3 vcc3.3 an4 rxsof[1] an5 vcc3.3 an6 rxfa[1] an7 vcc3.3 an8 rxenb[1] an9 vcc3.3 an10 rxaddr[2] an11 vcc3.3 an12 rsvd[2] an13 vcc3.3 an14 rxdata[18] an15 vcc3.3 an16 rxfa[2] an17 vcc3.3 an18 vcca an19 vcc3.3 an20 pci_gnt_l[1] an21 vcc3.3 an22 pci_cbe_l[3] an23 vcc3.3 an24 pci_frame_l an25 vcc3.3 an26 pci_ad[14] an27 vcc3.3 an28 pci_ad[4] an29 vcc3.3 an30 pci_par64 an31 vcc3.3 an32 pci_ad[55] an33 vcc3.3 an34 pci_ad[46] ball location signal name an35 vcc3.3 an36 pci_ad[36] an37 vcc3.3 ap1 rxprty[0] ap2 rxdata[3] ap3 rxdata[2] ap4 rxdata[5] ap5 rxdata[10] ap6 rxdata[1] ap7 rxdata[11] ap8 rxclk01 ap9 rxclk23 ap10 rxaddr[0] ap11 rxenb[0] ap12 rxdata[21] ap13 rxdata[17] ap14 rxdata[27] ap15 rxval[3] ap16 rxeof[2] ap17 rxprty[2] ap18 vcca ap19 pci_req_l[0] ap20 pci_inta_l ap21 pci_ad[29] ap22 pci_ad[24] ap23 pci_ad[20] ap24 pci_cbe_l[2] ap25 pci_stop_l ap26 pci_ad[15] ap27 pci_ad[9] ap28 pci_ad[5] ap29 pci_ad[0] ap30 pci_ack64_l ap31 pci_ad[60] ap32 pci_ad[56] ap33 pci_ad[51] ap34 pci_ad[47] ap35 pci_ad[41] ball location signal name
IXP2400 network processor 90 datasheet ap36 pci_ad[37] ap37 pci_ad[32] ar1 rxeof[1] ar2 vss ar3 rxdata[6] ar4 vss ar5 rxdata[13] ar6 vss ar7 rxdata[4] ar8 vss ar9 rxenb[3] ar10 vss ar11 rxdata[23] ar12 vss ar13 rxdata[20] ar14 vss ar15 rxfa[3] ar16 vss ar17 rxeof[3] ar18 sys_clk ar19 vss ar20 pci_gnt_l[0] ar21 pci_ad[30] ar22 vss ar23 pci_ad[21] ar24 vss ar25 pci_devsel_l ar26 vss ar27 pci_ad[10] ar28 vss ar29 pci_ad[1] ar30 vss ar31 pci_req64_l ar32 vss ar33 pci_ad[52] ar34 vss ar35 pci_ad[42] ar36 vss ball location signal name ar37 pci_ad[33] at1 rxfa[0] at2 rxpfa at3 rxdata[0] at4 rxdata[7] at5 rxdata[8] at6 rxdata[9] at7 rxdata[12] at8 rxdata[15] at9 txcsrb at10 rxdata[19] at11 rxdata[26] at12 rxdata[22] at13 rxdata[25] at14 rxdata[30] at15 rxdata[29] at16 rxerr[2] at17 rxerr[3] at18 vssa at19 pci_clk at20 vss at21 pci_ad[31] at22 pci_ad[25] at23 pci_ad[22] at24 pci_ad[16] at25 pci_trdy_l at26 pci_cbe_l[1] at27 pci_ad[11] at28 pci_ad[6] at29 pci_ad[2] at30 pci_cbe_l[4] at31 pci_ad[61] at32 pci_ad[57] at33 pci_ad[53] at34 pci_ad[48] at35 pci_ad[43] at36 pci_ad[38] at37 pci_ad[34] ball location signal name au1 vcc3.3 au2 rxpadl[1] au3 vcc3.3 au4 rxdata[14] au5 vcc3.3 au6 txcdata[3] au7 vcc3.3 au8 rxrcomp au9 vcc3.3 au10 rxdata[24] au11 vcc3.3 au12 rxdata[28] au13 vcc3.3 au14 rxdata[31] au15 vcc3.3 au16 rxprty[3] au17 vcc3.3 au21 vcc3.3 au22 pci_ad[26] au23 pci_ad[23] au24 pci_ad[17] au25 vcc3.3 au26 pci_par au27 pci_ad[12] au28 pci_ad[7] au29 vcc3.3 au30 pci_cbe_l[5] au31 pci_ad[62] au32 pci_ad[58] au33 vcc3.3 au34 pci_ad[49] au35 pci_ad[44] au36 pci_rcomp au37 vcc3.3 b1 d_ba[1] b2 d_ecc[3] b3 vss b4 d_dqs[8] ball location signal name
IXP2400 network processor datasheet 91 b5 d_ecc[2] b6 vcc2.5 b7 d_a[3] b8 d_a[11] b9 vss b10 d_a[9] b11 d_dq[22] b12 vcc2.5 b13 d_dqs[0] b14 d_dq[2] b15 vss b16 d_cke[0] b17 d_dq[3] b18 vcc2.5 b19 vss b20 vcc1.5 b21 s0_di[10] b22 vcc1.5 b23 s0_di[15] b24 vcc1.5 b25 s0_a[20] b26 vcc1.5 b27 s0_a[14] b28 vcc1.5 b29 s0_a[15] b30 vcc1.5 b31 s0_k[1] b32 vcc1.5 b33 s0_bwe_l[0] b34 vcc1.5 b35 s0_do[13] b36 vcc1.5 b37 vss c1 vss c2 d_dqs[4] c3 d_dq[37] c4 vcc2.5 c5 d_dm[8] ball location signal name c6 d_ecc[4] c7 vss c8 d_dq[19] c9 d_dqs[2] c10 vcc2.5 c11 d_dq[17] c12 d_dm[0] c13 vss c14 d_dq[8] c15 d_dq[10] c16 vcc2.5 c17 d_dq[7] c18 d_dq[0] c19 s0_di[12] c20 s0_di[9] c21 s0_di[6] c22 s0_cin[1] c23 s0_pi[1] c24 s0_di[3] c25 s0_a[17] c26 s0_a[12] c27 s0_a[1] c28 s0_a[16] c29 s0_a[21] c30 s0_k_l[0] c31 s0_k[0] c32 s0_k_l[1] c33 s0_rpe_l[1] c34 s0_wpe_l[0] c35 s0_do[8] c36 s0_do[5] c37 s0_wpe_l[1] d1 d_a[10] d2 vcc2.5 d3 d_dq[32] d4 d_ba[0] d5 vss d6 d_dm[3] ball location signal name d7 d_dq[26] d8 vcc2.5 d9 d_a[8] d10 d_dq[18] d11 vss d12 d_dq[21] d13 d_dq[14] d14 vcc2.5 d15 d_dq[20] d16 d_dq[13] d17 vss d18 d_a[13] d19 vss d20 s0_cin_l[0] d21 vss d22 s0_di[5] d23 vss d24 s0_a[22] d25 vss d26 s0_a[5] d27 vss d28 s0_a[13] d29 vss d30 s0_rpe_l[0] d31 vss d32 s0_do[12] d33 vss d34 s0_do[9] d35 vss d36 s0_do[4] d37 vss e1 d_we_l e2 d_ras_l e3 vss e4 d_dq[33] e5 d_a[0] e6 vcc2.5 e7 d_dq[30] ball location signal name
IXP2400 network processor 92 datasheet e8 d_dqs[3] e9 vss e10 d_dq[28] e11 d_dq[24] e12 vcc2.5 e13 d_dm[2] e14 d_dqs[1] e15 vss e16 d_dq[9] e17 d_dq[6] e18 vcc2.5 e19 s0_di[13] e20 vcc1.5 e21 s0_cin[0] e22 vcc1.5 e23 s0_di[2] e24 vcc1.5 e25 s0_a[10] e26 vcc1.5 e27 s0_a[0] e28 vcc1.5 e29 s0_c_l[0] e30 vcc1.5 e31 s0_do[14] e32 vcc1.5 e33 s0_do[15] e34 vcc1.5 e35 s0_do[10] e36 vcc1.5 e37 s1_vref f1 vss f2 d_cs_l[0] f3 d_dq[35] f4 vcc2.5 f5 d_dq[36] f6 d_dq[34] f7 vss f8 d_ck[0] ball location signal name f9 d_ecc[5] f10 vcc2.5 f11 d_a[6] f12 d_dq[29] f13 vss f14 d_dq[16] f15 d_cke[1] f16 vcc2.5 f17 d_dm[1] f18 d_ck[1] f19 s0_di[11] f20 s0_cin_l[1] f21 s0_pi[0] f22 s0_di[4] f23 s0_di[1] f24 s0_a[11] f25 s0_a[6] f26 s0_a[4] f27 s0_a[7] f28 s0_a[8] f29 s0_c[0] f30 s0_do[11] f31 vss f32 s0_do[3] f33 vcc1.5 f34 s0_do[6] f35 vss f36 s0_po[0] f37 vss g1 d_rcomp[0] g2 vcc2.5 g3 d_dq[41] g4 d_dq[40] g5 vss g6 d_dq[45] g7 d_dq[39] g8 vcc2.5 g9 d_ck_l[0] ball location signal name g10 d_a[2] g11 vss g12 d_a[1] g13 d_a[5] g14 vcc2.5 g15 d_a[12] g16 d_dq[12] g17 vss g18 d_ck_l[1] g19 vss g20 s0_di[8] g21 vss g22 s0_di[7] g23 vss g24 s0_a[9] g25 vss g26 s0_a[3] g27 vss g28 s0_do[0] g29 vss g30 vcc1.5 g31 s0_do[1] g32 vss g33 s0_do[2] g34 vss g35 s0_do[7] g36 vcc1.5 g37 vss h1 d_rcomp[1] h2 d_dqs[5] h3 vss h4 d_dm[5] h5 d_dq[43] h6 vcc2.5 h7 d_dq[44] h8 d_dm[4] h9 vss h10 d_ecc[0] ball location signal name
IXP2400 network processor datasheet 93 h11 d_ecc[1] h12 vcc2.5 h13 d_dq[31] h14 d_dq[27] h15 vss h16 d_dq[11] h17 d_dq[15] h18 vcc2.5 h19 s0_di[14] h20 vcc1.5 h21 vss h22 vcc1.5 h23 s0_di[0] h24 vcc1.5 h25 s0_a[2] h26 vcc1.5 h27 s0_bwe_l[1] h28 vcc1.5 h29 s0_zq[1] h30 s1_di[12] h31 vcc1.5 h32 s1_di[13] h33 vcc1.5 h34 s1_di[9] h35 s1_di[10] h36 vss h37 vss j1 vss j2 d_dq[46] j3 d_dq[51] j4 vcc2.5 j5 d_dq[53] j6 d_dq[48] j7 vss j8 d_dq[42] j9 d_dq[38] j10 vss j11 vcc ball location signal name j12 vss j13 vcc j14 vss j15 vcc j16 vss j17 vcc j18 thermda j19 thermdc j20 vss j21 vcc j22 vss j23 vcc j24 vss j25 vcc j26 vss j27 vcc j28 vss j29 vcc j30 s0_zq[0] j31 vss j32 s1_di[14] j33 s1_di[11] j34 vss j35 s1_di[8] j36 s1_cin_l[0] j37 vss k1 d_cs_l[1] k2 vcc2.5 k3 d_dqs[6] k4 d_dq[55] k5 vss k6 d_dm[6] k7 d_cas_l k8 vcc2.5 k9 vss k10 vcc k11 vss k12 vcc ball location signal name k13 vss k14 vcc k15 vss k16 vcc k17 vss k18 vcc k19 vss k20 vcc k21 vss k22 vcc k23 vss k24 vcc k25 vss k26 vcc k27 vss k28 vcc k29 vss k30 vcc1.5 k31 s1_di[15] k32 s1_di[6] k33 vcc1.5 k34 s1_di[5] k35 s1_cin[1] k36 vcc1.5 k37 s1_di[3] l1 d_dq[56] l2 d_dq[47] l3 vss l4 d_dq[54] l5 d_dq[50] l6 vcc2.5 l7 d_dq[49] l8 d_dq[52] l9 vcc l10 vss l11 vcc l12 vss l13 vcc ball location signal name
IXP2400 network processor 94 datasheet l14 vss l15 vcc l16 vss l17 vcc l18 vss l19 vcc l20 vss l21 vcc l22 vss l23 vcc l24 vss l25 vcc l26 vss l27 vcc l28 vss l29 vcc l30 s1_pi[0] l31 vss l32 s1_di[7] l33 s1_cin[0] l34 vss l35 s1_cin_l[1] l36 s1_pi[1] l37 vss m1 vss m2 d_dq[59] m3 d_dq[58] m4 vcc2.5 m5 d_dq[62] m6 d_dqs[7] m7 vss m8 d_dq[57] m9 vss m10 vcc m11 vss m12 vcc m13 vss m14 vcc ball location signal name m15 vss m16 vcc m17 vss m18 vcc m19 vss m20 vcc m21 vss m22 vcc m23 vss m24 vcc m25 vss m26 vcc m27 vss m28 vcc m29 vss m30 vcc1.5 m31 s1_a[23] m32 s1_di[0] m33 vcc1.5 m34 s1_di[2] m35 s1_di[4] m36 vcc1.5 m37 vss n1 d_dq[61] n2 vcc2.5 n3 d_ck[2] n4 d_ck_l[2] n5 vss n6 d_dq[60] n7 d_dm[7] n8 vcc2.5 n9 vcc n10 vss n11 vcc n12 vss n13 vcc n14 vss n15 vcc ball location signal name n16 vss n17 vcc n18 vss n19 vcc n20 vss n21 vcc n22 vss n23 vcc n24 vss n25 vcc n26 vss n27 vcc n28 vss n29 vcc n30 s1_a[20] n31 vss n32 s1_a[21] n33 s1_a[22] n34 vss n35 s1_a[18] n36 s1_a[19] n37 vss p1 d_vref[1] p2 d_dq[63] p3 vss p4 d_rcvenout_l p5 d_rcvenin_l p6 vcc2.5 p7 vss p8 vss p9 vss p10 vcc p11 vss p12 vcc p13 vss p14 vcc p15 vss p16 vcc ball location signal name
IXP2400 network processor datasheet 95 p17 vss p18 vcc p19 vss p20 vcc p21 vss p22 vcc p23 vss p24 vcc p25 vss p26 vcc p27 vss p28 vcc p29 vss p30 vcc1.5 p31 s1_a[16] p32 s1_a[17] p33 vcc1.5 p34 s1_a[14] p35 s1_a[15] p36 vcc1.5 p37 s1_di[1] r1 vss r2 vcc2.5 r3 vss r4 vcc2.5 r5 vss r6 vss r7 vss r8 vss r9 vcc r10 vss r11 vcc r12 vss r13 vcc r14 vss r15 vcc r16 vss r17 vcc ball location signal name r18 vss r19 vcc r20 vss r21 vcc r22 vss r23 vcc r24 vss r25 vcc r26 vss r27 vcc r28 vss r29 vcc r30 s1_a[12] r31 vss r32 s1_a[13] r33 s1_a[6] r34 vss r35 s1_a[10] r36 s1_a[11] r37 vss t1 vss t2 vss t3 vss t4 vss t5 vss t6 vss t7 vss t8 vss t9 vss t10 vcc t11 vss t12 vcc t13 vss t14 vcc t15 vss t16 vcc t17 vss t18 vcc ball location signal name t19 vss t20 vcc t21 vss t22 vcc t23 vss t24 vcc t25 vss t26 vcc t27 vss t28 vcc t29 vss t30 vcc1.5 t31 s1_a[7] t32 s1_a[8] t33 vcc1.5 t34 s1_a[9] t35 s1_a[1] t36 vcc1.5 t37 s1_a[5] u1 vss u2 vss u3 vss u4 vss u5 vss u6 vss u7 vss u8 vss u9 vcc u10 vss u11 vcc u12 vss u13 vcc u14 vss u15 vcc u16 vss u17 vcc u18 vss u19 vcc ball location signal name
IXP2400 network processor 96 datasheet u20 vss u21 vcc u22 vss u23 vcc u24 vss u25 vcc u26 vss u27 vcc u28 vss u29 vcc u30 s1_bwe_l[0] u31 vss u32 s1_k_l[0] u33 s1_a[4] u34 vss u35 s1_c_l[1] u36 s1_a[0] u37 vss v2 txprty[3] v3 vcc3.3 v4 txenb[3] v5 vcc3.3 v6 txerr[3] v7 vcc3.3 v8 vss v9 vss v10 vcc v11 vss v12 vcc v13 vss v14 vcc v15 vss v16 vcc v17 vss v18 vcc v19 vss v20 vcc v21 vss ball location signal name v22 vcc v23 vss v24 vcc v25 vss v26 vcc v27 vss v28 vcc v29 vss v30 vcc1.5 v31 s1_c_l[0] v32 s1_a[2] v33 vcc1.5 v34 s1_a[3] v35 s1_k[1] v36 vcc1.5 w2 vss w3 txprty[2] w4 vss w5 txsof[3] w6 vss w7 txeof[3] w8 vss w9 vcc w10 vss w11 vcc w12 vss w13 vcc w14 vss w15 vcc w16 vss w17 vcc w18 vss w19 vcc w20 vss w21 vcc w22 vss w23 vcc w24 vss ball location signal name w25 vcc w26 vss w27 vcc w28 vss w29 vcc w30 s1_do[3] w31 vss w32 s1_bwe_l[1] w33 s1_do[15] w34 vss w35 s1_c[0] w36 s1_c[1] y2 txdata[27] y3 txenb[2] y4 txdata[28] y5 txerr[2] y6 txdata[31] y7 txsof[2] y8 txeof[2] y9 vss y10 vcc y11 vss y12 vcc y13 vss y14 vcc y15 vss y16 vcc y17 vss y18 vcc y19 vss y20 vcc y21 vss y22 vcc y23 vss y24 vcc y25 vss y26 vcc y27 vss ball location signal name
IXP2400 network processor datasheet 97 y28 vcc y29 vss y30 vcc1.5 y31 s1_do[9] y32 s1_do[12] y33 vcc1.5 y34 s1_do[13] y35 s1_po[1] y36 vcc1.5 ball location signal name
intel ? IXP2400 network processor 98 datasheet 4.0 electrical specifications this chapter specifies the following electrical behavior of the IXP2400: absolute maximum ratings dc values and ac timing specifications for the following: ? pci i/o unit ?qdr ?ddr sdram ?c bus ? pos-phy and csix ? slowport i/o buffer ?gpio ?jtag ? serial port 4.1 absolute maximum ratings operating beyond the functional operating temperature ranges shown in table 33 is not recommended and extended exposure beyond the functional operating temperature range may affect reliability. table 34 lists the functional operating voltage range. table 33. functional operating temperature range parameter minimum maximum maximum junction temperature comment commercial temperature operating range 0c 70c 120c refer to the IXP2400 network processor thermal design considerations application note . extended temperature operating range -40c 85c refer to the IXP2400 network processor thermal design considerations application note .
intel ? IXP2400 network processor datasheet 99 the measurements shown in table 36 were taken by running a reference application (ipv4 forwarding + qos) at oc-48 line rate w ith worst-case minimum size 48-byte packets. the values in table 37 are used for the board design on each power rail. the measurements were taken by running synthetic tests that maximize the activity factors for a particular power supply rail, one rail at a time, and are expected to re flect the worst-case power consumption for each power supply rail under artificial conditions. table 34. functional operating voltage range supply name vo lt ag e (v ) 400 mhz (b stepping) voltag e (v) 600 mhz (a and b stepping) tolerance comments vcc1.3 1.1 1 1. for a-stepping (400-mhz) IXP2400, vcc1.3 and vcca1.3 is 1.3v. 1.30 5% core supply for the IXP2400 vcca1.3 1.1 1 1.30 5% pll supply: isolated from core. low current. vcc2.5 2.5 2.5 5% ddr sdram interface supply vcc1.5 1.50 1.50 3% qdr sram interface supply vcc3.3 3.3 3.3 5% media switch fabric, pci and misc. table 35. power totals for b stepping operating frequency typical 1 1. typical values are based on a full-duplex 2g ethernet design with one qdr channel used. maximum units 400 mhz 9.3 11.52 w 600 mhz 12.85 16.05 w table 36. maximum power for thermal solution 1 1. values presented include core and i/o. supply name a stepping b stepping units 400 mhz (1.3v) 600 mhz (1.3v) 400 mhz (1.1v) 2 2. 400-mhz (b stepping) IXP2400 devices should use a 1.1v core power supply; 600-mhz IXP2400 devices can only use a 1.3v core power supply. 600 mhz (1.3v) vcc1.3 7.41 11.05 4.4 8.26 w vcca1.3 vcc1.5 3 3. qdr and ddr i/o values include power consumption from termination. 2.03 2.03 2.25 2.25 w vcc2.5 3 2.30 2.30 1.75 1.75 w vcc3.3 2.45 2.45 2.45 2.45 w totals 14.19 17.83 10.85 14.71 w
intel ? IXP2400 network processor 100 datasheet 4.1.1 reducing power consumption the following are recommendations to help reduce power consumption: don?t connect unused qdr channels (remove any termination for the channel; do not connect anything to it). if only one or two sram chips suffice for an application and the board design allows the IXP2400 and the sram chips to be close to each other, termination can be removed or termination resistance can be increased. for instance, on boards that demonstrate good signal integrity and have the IXP2400 and sram chips placed within two inches of each other, there may be no need for termination. use only as much of the 32-bit msf inte rface as needed; this minimizes the power consumption at the unused sub-channels. table 37. maximum power consumption by power supply 1 1. values presented include core and i/o. supply name a stepping b stepping units 400 mhz (1.3v) 600 mhz (1.3v) 400 mhz (1.1v) 2 2. 400-mhz (b stepping) IXP2400 devices should use a 1.1v core power supply; 600-mhz IXP2400 devices can only use a 1.3v core power supply. 600 mhz (1.3v) vcc1.3 8.92 13.62 4.46 8.59 w vcca1.3 vcc1.5 3 3. qdr and ddr i/o values include po wer consumption from termination. 2.67 2.67 2.34 2.49 w vcc2.5 3 3.15 3.15 1.75 2.00 w vcc3.3 2.97 2.97 2.97 2.97 w totals 17.71 22.41 11.52 16.05 w figure 12. pll power supply connection b0549-01 22 f 1.5 inches vssa vcca 1.3 pll 4.7 h vcca 1.3 intel ? IXP2400 network processor
intel ? IXP2400 network processor datasheet 101 use only 32-bit and/or 33-mhz pci if it is adequate for the application. power consumption in such cases is lower than pci 64-bit/66-mhz. 4.2 ac/dc specifications 4.2.1 clock timing specifications 1. these specifications apply only to sys_clk and are very preliminary estimates. 2. 0.2 x vcc3.3 to 0.6 x vcc3.3. 3. when the IXP2400 powers up, the reference clock should start running as soon as possible. 4.2.2 pci i/o unit this section specifies the following el ectrical behavior for the pci i/o unit. figure 13. sys_clk timing table 38. sys_clk dc specification symbol parameter minimum maximum maximum duration unit v il input low voltage 0 0.5 ? v v ih input high voltage 2.4 3.3 ? v vov overshoot 0 0.2 3% of sys_clk cycle v vus undershoot -0.2 0 v table 39. sys_clk ac specifications symbol parameter min typical max unit sys_clk 1 reference clock frequency 66 ? 100 mhz t cyc sys_clk cycle time 10 ? 16.6 ns t high sys_clk high time 4.2 ? ? ns t low sys_clk low time 4.2 ? ? ns ? sys_clk slew rate 2 2?4v/ns a9816-01 t cyc vil vih t high t low
intel ? IXP2400 network processor 102 datasheet absolute maximum ratings dc specifications ac timing specifications 4.2.2.1 pci absolute maximum ratings the power specifications listed in table 41 are based on the following assumption: pci bus frequency (pci_clk) = 66 mhz. 1. typical power measured at nominal supply voltages. the power consumption from the 1.3v supply is very low and will be ignored. 4.2.2.2 pci dc specifications in table 42 , currents into the chip (chip sinking) are denoted as positive (+) current. currents from the chip (chip sourcing) are denoted as negative (-) current. input leakage currents include high-z output leakage for all bidirectional buffers with tr i-state outputs. these el ectrical specifications are preliminary and subject to change. 1. input leakage currents include high-impedance output leakage for all bidirectional buffers with tri-state outputs. 4.2.2.3 pci overshoot/undershoot specifications the pci i/os are designed to tolerate overshoo t and undershoot associated with normal i/o switching. however, excessive overshoot or undershoot of i/o signals can cause the device to latchup. table 43 specifies limits on i/o overshoot and undershoot that should never be exceeded. table 40. absolute maximum pci ratings parameter minimum maximum comment maximum voltage applied to signal pins -0.3 v 3.6 v supply voltage (i/o), vcc3.3 3.0 v 3.6 v 3.3 v supply table 41. pci typical and maximum power parameter typical 1 maximum comment vcc3.3 0.37 w 0.92 w 3.3 v supply table 42. pci dc specifications symbol parameter condition minimum maximum v ih input high voltage ? 0.5 x vcc3.3 vcc3.3 + 0.5 v v il input low voltage ? ? 0.3 x vcc3.3 v oh output high voltage ioh = -0.5 ma 0.9 x vcc3.3 ? v ol output low voltage iol = 1.5 ma ? 0.1 x vcc3.3 i i input leakage current 1 0 intel ? IXP2400 network processor datasheet 103 4.2.2.4 pci ac specifications the ac specifications consist of input requirements and output responses. the input requirements consist of setup and hold times, pulse widths, and high and low times. output responses are delays from clock to signal. the pci pins support the basic set of pci electrical specifications in the pci local bus specification, revision 2.2 . see that document for a complete description of the pci i/o protocol and pin ac specifications. 4.2.2.5 pci clock signal ac parameter measurements vt1 = 0.5*vcc3.3 vt2 = 0.4*vcc3.3 vt3 = 0.3*vcc3.3 1. 0.3 vcc3.3 to 0.6 vcc3.3 table 43. overshoot/undershoot specifications pin type undershoot overshoot maximum duration input vss ? 1v vcc3.3 + 1v 6 ns output vss ? 0.74v vcc3.3 + 0.74v 4 ns bidirectional vss ? 0.74v vcc3.3 + 0.74v 4 ns figure 14. pci clock signal ac parameter measurements i a9817-02 t cyc v t3 v t1 v t2 t high t low table 44. 66-mhz pci clock signal ac parameters symbol parameter minimum maximum unit t cyc pci_clk cycle time 15 ns t high pci_clk high time 6 ? ns t low pci_clk low time 6 ? ns ? pci_clk slew rate 1 1.5 4 v/ns
intel ? IXP2400 network processor 104 datasheet 1. 0.3 vcc3.3 to 0.6 vcc3.3. 4.2.2.6 pci bus signals timing 1. point-to-point signals are req_l, gnt_l. 2. the setup time is measured with a 1?4v/ns input slew rate. table 45. 33-mhz pci clock signal ac parameters symbol parameter minimum maximum unit t cyc pci_clk cycle time 30 ? ns t high pci_clk high time 11 ? ns t low pci_clk low time 11 ? ns ? pci_clk slew rate 1 14v/ns figure 15. pci bus signals table 46. 33-mhz pci signal timing symbol parameter minimum maximum unit t val clk to signal valid delay, bused signals 2 11 ns t val (point-to-point) clk to signal valid delay, point-to-point signals 1 212ns t on float to active delay 2 ? ns t off active to float delay ? 28 ns t su 2 input setup time to clk, bused signals 3 7?ns t su (point-to-point) input setup time to clk, point-to-point signals (gnt_l) 1 10 ? ns t su (point-to-point) input setup time to clk, point-to-point signals (req_l) 1 12 ? ns t h 4 input signal hold time from clk 0.5 ? ns a9393-01 t val(max) t su t h t val(min) t on t off v test pci_clk outputs inputs note: v test = 0.4 vcc3.3 for 3.3 volt pci signals
intel ? IXP2400 network processor datasheet 105 3. bused signals are ad, cbe_l, par, perr_l, serr_l, frame_l, irdy_l, trdy_l, devsel_l, stop_l 4. these parameters are at variance with those in the pci local bus specification, revision 2.2 . 1. point-to-point signals are req_l, gnt_l. 2. the setup time is measured with a 1?4v/ns input slew rate. 3. bused signals are ad, cbe_l, par, perr_l, serr_l, frame_l, irdy_l, trdy_l, devsel_l, stop_l. 4. these parameters are at variance with those in the pci local bus specification, revision 2.2 . 4.2.3 sram please note that the data presented in table 48 was gathered using a load circuit with attributes as shown in figure 16 . table 47. 66-mhz pci signal timing symbol parameter minimum maximum unit t val clk to signal valid delay, bused signals 2 6 ns t val (point-to-point) clk to signal valid delay, point-to-point signals 1 26ns t on float to active delay 2 ? ns t off active to float delay ? ? ns t su 2 input setup time to clk, bused signals 3 3?ns t su (point-to-point) input setup time to clk, point-to-point signals 1 5?ns t h 4 input signal hold time from clk 0.5 ? ns table 48. qdr dc specifications symbol parameter conditions minimum maximum unit notes v ih input high voltage (logic 1) ? vref + 0.1 vcc1.5 + 0.1 v 3 v il input low voltage (logic 0) ? -0.1 vref - 0.1 v 3 i li input leakage current 0v vin vcc1.5 0 20 a i lo output leakage current output(s) disabled, 0v vin vcc1.5 020a v oh (low current) output high voltage |ioh| 0.1 ma (when the i/o is tristated) vcc1.5/2 - 0.2 vcc1.5/2 + 0.2 v 3, 5 v oh note 1 vcc1.5 x .75 - 0.1 vcc1.5 x .75 - 0.1 v3, 5 v ol (low current) output low voltage |iol| 0.1 ma (when the i/o is tristated) vcc1.5/2 - 0.2 vcc1.5/2 + 0.2 v 3, 5 v ol note 2 vcc1.5/4 - 0.1 vcc1.5/4 + 0.1 v 3, 5 vcc1.5 isolated output buffer supply ? 1.4 1.6 v 3 v ref reference voltage ? 0.7 0.8 v 3 notes: 1. outputs are impedance-controlled. | ioh | = (vcc1.5/2)/(rz) for values of rz = 50 ohms. 2. outputs are impedance-controlled. iol = (vcc1.5/2)/((rz) for values of rz = 50 ohms. 3. all voltages referenced to vss (gnd). 4. ac load current is higher than the shown dc values. ac i/o (ibis model) curves are available in the ixa hdk2400. 5. hstl outputs meet jedec hstl class i and class ii standards.
intel ? IXP2400 network processor 106 datasheet figure 17 illustrates the timing goals for the IXP2400 qdr ii interface. for qdr, it is necessary to delay the input clock appropriately to acheive th e required setup and hold time. for example, for qdr at 100 mhz, delay the input clock by 2.1 ns compared to data. the clock will be shifted by 2.5 ns by internal dll and hence strobe for the data at 4.6 ns. figure 16. qdr load circuit table 49. qdr and qdrii signal timing parameters symbol parameter qdrii (200 mhz) qdr/qdrii (150 mhz) qdr/qdrii (133 mhz) qdr/qdrii (100 mhz) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) tcycle clock cycle time 5.0 ? 6.6 ? 7.5 ? 10.0 ? tvalmin tval clock to data output valid (k/k#) 0.85 ? 1.25 ? 1.25 ? 1.95 ? tvalmax ? 0.85 ? 1.25 ? 1.25 ? 1.95 tval_a_ min clock to r/w control output valid and address 1 1. if reference k clock any given pins, including data and controls, the maximum skew is 300 psec. 0.85 ? 1.25 ? 1.25 ? 1.95 ? tval_a_ max ? 0.85 ? 1.25 ? 1.25 ? 1.95 tsu tsu 2 (setup time) 2. the setup time is measured before the rising edge of the clock; when the measurements for tsu are prefaced by a minus sym- bol (?-?), the data is actually after the rising edge of the cl ock. when the measurements for tsu are prefaced by a plus symbol (?+?), the data is actually before the rising edge of the clock. the setup time is measured with 1v/ns input slew rate. ? -0.60 ? -0.95 ? -1.0 ? -1.7 th th (hold time) 1.80 ? 2.35 ? 2.5 ? 2.8 ? tjt clock cycle-to-cycle jitter 100 psec ? 150 psec ? 150 psec ? 200 psec ? ? c/c# duty cycle 2.4 2.6 3.2 3.4 3.65 3.85 4.9 5.1 ? k/k# duty cycle 2.4 2.6 3.2 3.4 3.65 3.85 4.9 5.1 b0058-01 rz = 50 ? rz = 50 ? rz = 50 ? vref vcc1.5 vcc1.5/2 intel ? IXP2400 network processor do zq[1] zq[0]
intel ? IXP2400 network processor datasheet 107 4.2.4 ddr sdram table 50 lists the ddr sdram dc parameters. table 51 lists the ac parameters. figure 17. qdrii timing reference b1257-01 k k# a/r#/w# q d c 12345678910 c# t cyde t cyde t su t su t val_a_min t val_min t h t h t val_a_max t val_max table 50. ddr sdram dc parameters for 100/150 mhz symbol parameter minimum maximum unit v dref ddr reference voltage 0.48 x vcc2.5 0.52 x vcc2.5 ? v oh output high voltage vcc2.5 x .75 - 0.15 vcc2.5 x .75 + 0.15 v v ol output low voltage vcc2.5/4 - 0.15 vcc2.5/4 + 0.15 v i oh output high current 18 22 ma i ol output low current 18 22 ma i leak input leakage current -10 +10 a vil (dc) input low voltage, dc ? vdref - 0.15 v vih (dc) ddr input high voltage, dc vdref + 0.15 ? v
intel ? IXP2400 network processor 108 datasheet vil (ac) ddr input low voltage, ac ? vdref - 0.31 v vih (ac) ddr input high voltage, ac vdref + 0.31 ? v c io ddr input/output pin capacitance 4.690 5.370 pf table 51. ddr sdram ac parameters for 100/150 mhz symbol parameter 150 mhz 100 mhz unit min max min max tck d_ck period 6.6 ? 10 ? ns tck (high) d_ck high time 3.11 ? 4.67 ? ns tck (low) d_ck low time 3.19 ? 4.79 ? ns tjt (jitter time) d_ck cycle to cycle ? 132 ? 198 psec t skew tdqsck skew between any system memory differential clock pair ? + or - 170 (340 total) ? + or - 255 (510 total) psec t ckvb d_ras_l, d_cas_l, d_we_l, d_a[12:0], d_ba[1:0]. valid before ck rising edge 2.50 ? 3.99 ? ns t ckva d_ras_l, d_cas_l, d_we_l, d_a[12:0], d_ba[1:0]. valid 3.10 ? 3.49 ? ns t cke_vb d_cke_[1:0]. valid before d_ck rising edge 2.50 ? 3.99 ? ns t cke_va d_cke_[1:0]. valid after d_ck rising edge 3.10 ? 3.49 ? ns t cs_vb d_dm_[8:0], d_unused_cs_l_2, d_cs_l[1:0]. valid before d_dqs rising edge 2.50 ? 3.99 ? ns t cs_va d_dm_[8:0], d_unused_cs_l_2, d_cs_l[1:0]. valid after d_dqs rising edge 3.10 ? 3.49 ? ns t dvb d_dq[63:0], d_ecc[7:0] valid before d_dqs[1:0] rising or falling edge 0.95 ? 1.25 ? ns t dva d_dq[63:0], d_ecc[7:0] valid after d_dqs[1:0] rising or falling edge 0.95 ? 1.25 ? ns t su d_dq and d_ecc input setup time to d_dqs rising or falling edge -0.9 -0.7 ns t hd d_dq and d_ecc input hold time to d_dqs rising or falling edge 2.5 ? 3.5 ? ns t dss d_dqs falling edge output access time to d_ck rising edge 2.77 ? 4.16 ? ns t dsh d_dqs falling edge output access time from d_ck rising edge 2.80 ? 4.21 ? ns t wpre d_dqs write preamble duration 4.65 ? 6.98 ? ns table 50. ddr sdram dc parameters for 100/150 mhz (continued) symbol parameter minimum maximum unit
intel ? IXP2400 network processor datasheet 109 4.2.4.1 ac timing diagrams this section provides the ac timing diagrams for the ddr sdram interface. t wpst d_dqs write postamble duration 3.19 ? 4.78 ? ns t dqss d_ck rising edge output access time, where a write command is referenced, to the first d_dqs rising edge 5.99 7.08 8.99 10.61 ns t poe d_ck rising edge output access time, where a write command is referenced, to the d_dqs preamble falling edge ? 1.96 ? 2.94 ns t rcvenout d_ck rising edge output access time: a read command is referenced, to the d_rcvenout_l falling edge 9.45 (tcklow= 2.0) 12.78 (tcklow= 2.5) 10.31 (tcklow= 2.0) 13.64 (tcklow= 2.5) 14.17 (tcklow= 2.0) 19.17 (tcklow= 2.5) 15.47 (tcklow= 2.0) 20.47 (tcklow= 2.5) ns t surcv d_rcvenin_l falling edge setup time to the first d_dqs rising edge 3.13 ? 4.7 ? ns t hdrcv d_rcvenin_l falling edge hold time to the first d_dqs rising edge -0.87 ? -1.30 ? ns t prehdrev d_rcvenin_l falling edge hold time to the first d_dqs preamble falling edge -0.87 ? -1.30 ? ns table 51. ddr sdram ac parameters for 100/150 mhz (continued) symbol parameter 150 mhz 100 mhz unit min max min max figure 18. data and error correction setup/hold relationship to/from data strobe (read operation) a9819-01 t su t su t hd t hd valid data valid data valid data valid data 0.5xvcc2.5 d_dqs d_dq, d_ecc
intel ? IXP2400 network processor 110 datasheet figure 19. data and error correction valid before and after data strobe (write operation) a9820-01 t dvb t dva t dvb t dva 0.5xvcc2.5 d_dqs d_dq, d_ecc valid data valid data valid data valid data figure 20. write preamble duration a9821-01 t wpre 0.5xvcc2.5 d_dqs figure 21. write postamble duration a9822-01 t wpst 0.5xvcc2.5 d_dqs figure 22. command signals valid before and after clock rising edge a9823-01 t cvb t cva d_ck_l[2:0] d_ck[2:0] d_a[12:0], d_ba, d_ras_l, d_cas_l, d_we_l valid data
intel ? IXP2400 network processor datasheet 111 figure 23. clock enable valid before and after clock rising edge a9824-03 t cke_vb t cke_va d_ck_l[2:0] d_dqs d_cke[1:0] valid data figure 24. chip select valid before and after clock rising edge a9825-03 t cs_vb t cs_va d_dqs d_cs[1:0] d_dm[8:0] valid data figure 25. clock cycle time figure 26. skew between any system memory differential clock pair a9826-01 t ck d_ck_l[2:0] d_ck[2:0] a9827-01 t skew d_ck_lx d_ckx d_cky d_ck_ly
intel ? IXP2400 network processor 112 datasheet figure 27. clock high time a9828-01 t ch d_ck_l[2:0] d_ck[2:0] figure 28. clock low time a9829-01 t cl d_ck_l[2:0] d_ck[2:0] figure 29. data strobe falling edge output access time to clock rising edge a9830-01 t dss d_ck_l[2:0] d_ck[2:0] d_dqs 0.5xvcc2.5 figure 30. data strobe falling edge output access time from clock rising edge a9831-01 t dsh d_ck_l[2:0] d_ck[2:0] d_dqs 0.5xvcc2.5
intel ? IXP2400 network processor datasheet 113 figure 31. clock rising edge output access time to the first data strobe rising edge a9832-01 t dqss d_ck_l[2:0] d_ck[2:0] d_dqs d_a[12:0], d_ba, d_ras_l, d_cas_l, d_we_l write cmd 0.5xvcc2.5 figure 32. clock rising edge output access time to the data strobe preamble falling edge a9833-01 t poe d_ck_l[2:0] d_ck[2:0] d_dqs d_a[12:0], d_ba, d_ras_l, d_cas_l, d_we_l write cmd 0.5xvcc2.5 figure 33. clock rising edge output access time to output clock falling edge a9834-01 t d_rcvenout_l d_ck_l[2:0] d_ck[2:0] d_rcvenout_l d_a[12:0], d_ba, d_ras_l, d_cas_l, d_we_l read cmd 0.5xvcc2.5
intel ? IXP2400 network processor 114 datasheet 4.2.5 media and switch fabric (msf) interface this section describes the parameters for the msf interface. these parameters apply whether the bus is configured to carry either pos level 2/spi-3 packets/cells or utopia 1/2/3 csix c-frames. the msf interface can operate at a maximum of 133 mhz with a 600-mhz IXP2400, and at a maximum of 104 mhz with a 400-mhz IXP2400. figure 34. input clock falling edge setup time to the first data strobe rising edge a9835-01 t surcv d_dqs d_rcvenin_l 0.5xvcc2.5 0.5xvcc2.5 figure 35. input clock rising edge hold time from the first data strobe rising edge a9839-01 t hdrcv d_dqs d_rcvenin_l 0.5xvcc2.5 0.5xvcc2.5 figure 36. input clock falling edge hold time from the data strobe preamble falling edge a9840-01 tpre hdrcv d_dqs d_rcvenin_l 0.5xvcc2.5 0.5xvcc2.5
intel ? IXP2400 network processor datasheet 115 4.2.5.1 dc parameters table 52 lists applicable dc thresholds for the msf. ) 4.2.5.2 media clocks table 52. msf (lvttl) dc thresholds symbol parameter condition min max vih input high ? 2.0v ? vil input low ? ? 0.8v voh output ioh = -8 ma 2.4v ? vol output low iol = 8 ma ? 0.5v i leak input leakage current ? -10 a +10 a cload pin capacitance ? ? 10 pf table 53. msf overshoot/undershoot specifications pin type undershoot overshoot maximum duration input vss ? 1v vcc3.3 + 1v 6 ns output vss ? 0.74v vcc3.3 + 0.74v 4 ns figure 37. media clock timing table 54. media clock dc specification symbol parameter minimum typical maximum unit vl input low voltage 0 ? 0.8 v vh input high voltage 2.4 ? 3.3 v vov overshoot 0 ? 0.2 v vus undershoot -0.2 ? 0 v a9816-01 t cyc vil vih t high t low
intel ? IXP2400 network processor 116 datasheet 1. 0.3 vcc3.3 to 0.6 vcc3.3 2. includes rxclk01, rxclk23, and txclk01, txclk23. 4.2.5.3 ac parameters the IXP2400 supports the ixf6048 utopia level 3 (single 64-bit, 32-bit, or quad 8-bit), level 2 (single 8/16-bit), and level 1 (quad 8/16-bit) interface modes. figure 38 and figure 39 illustrate receive and transmit, respectively, utopia/pos/csix single interface, 32/16/8-bit databus, two clock cycl e decode-response delay and no high-impedance outputs. table 55. media clock ac specifications symbol parameter min typical max unit t cyc clk cycle time 8 ? 40 ns t high clk high time 3.4 ? ? ns t low clk low time 2 3.4 ? ? ns ? clk slew rate 1, 2 2?4v/ns table 56. media interface signal ac parameters symbol parameter 600-mhz IXP2400 (max of 150-mhz msf) 400-mhz IXP2400 (max of 104-mhz msf) unit min max min max unit t rxval01 output valid delay from rxclk01 1.2 3.4 1.2 3.6 ns t rxsu01 input setup time to rxclk01 1.0 ? 1.5 ? ns t rxh01 input hold time from rxclk01 0.3 ? 0.15 ? ns t rxval23 output valid delay from rxclk23 1.2 3.4 1.2 3.6 ns t rxsu23 input setup time to rxclk23 1.0 ? 1.5 ? ns t rxh23 input hold time from rxclk23 0.3 ? 0.15 ? ns t txval01 output valid delay from rxclk01 1.2 3.4 1.2 3.6 ns t txsu01 input setup time to rxclk01 1.0 ? 1.5 ? ns t txh01 input hold time from rxclk01 0.3 ? 0.15 ? ns t txval23 output valid delay from rxclk23 1.2 3.4 1.2 3.6 ns t txsu23 input setup time to rxclk23 1.0 ? 1.5 ? ns t txh23 input hold time from rxclk23 0.3 ? 0.15 ? ns
intel ? IXP2400 network processor datasheet 117 4.2.6 cbus table 57 lists applicable driver dc thresholds for the cbus. figure 38. receive utopia/pos/csix a9841-01 t rxsu t rxh t rxval t cyc 0.5xvcc3.3 rxclk01 rxclk23 rxeof, rxpadl, rxval, rxdata, rxprty, rxsof, rxderr, rxpfa, rxfa rxaddr, rxenb valid output valid output valid input valid input figure 39. transmit utopia/pos/csix a9842-01 t txsu t txh t txval t cyc 0.5xvcc3.3 txclk01 txclk23 txpfa, txsfa, txfa txdata, txprty, txsof, txaddr, txenb txeof, txpadl, txerr valid output valid output valid input valid input table 57. cbus (lvttl) driver dc specifications symbol parameter condition minimum maximum vih input high ? 2.0v ? vil input low ? ? 0.8v voh output ioh = -8 ma 2.4v ? vol output low iol = 8 ma 0.4v i leak input leakage current 0 intel ? IXP2400 network processor 118 datasheet 4.2.7 slowport, gpio, and serial i/o buffer table 58 lists the ac and dc parameters for the slow port and gpio. the gpio can be used with appropriate software in i 2 c application. refer to the philips semiconductor* i 2 c bus specification for the dc and ac characteristics. the serial port consists of txd, rxd, which are asynchronous relative to any device outside the IXP2400. 1. all voltages referenced to vss (gnd). 2. ac load current is higher than the shown dc values. 3. for cload greater than 20 pf or three or more devices, transceivers or clock buffers need to be used. table 59 timing applies to mode 0, 1, 2, 3, and 4. logic diagrams for these modes are presented in the intel IXP2400 hardware reference manual . table 58. slowport, gpio, and serial i/o buffer ac/dc specifications symbol parameter conditions minimum maximum unit notes vih input high (logic 1) voltage ? 2.0 vcc3.3 + 0.3 v ? vil input low (logic 0) voltage ? -0.3 0.8 v ? ili input leakage current ? -10.0 +10.0 a ? voh output high voltage ioh = -2.0 ma 2.4 ? v 1, 2 vol output low voltage iol = 2.0 ma ? 0.4 v 1, 2 tr slew rate rising cload = 10 pf 1.3 5.1 v/ns 3 tf slew rate falling cload = 10 pf 0.9 4.7 v/ns 3 tr slew rate rising cload = 20 pf 1.1 3.4 v/ns 3 tf slew rate falling cload = 20 pf 0.7 3.4 v/ns 3 cload pin capacitance ? 5 20 pf 3
intel ? IXP2400 network processor datasheet 119 table 60 timing applies to mode 0, 1, 2, 3, and 4. figure 40. mode 0 single write transfer for self-timing device ? slowport table 59. slowport write timing external signals tco rise (default 1 ) (ns) 1. default out timing delay is controlled by the txe regist er. by default, this register is set to 1, i.e., two p clock cycles delay or 6666.66 psec. minimum delay can be set to 0. tco fall (default 2 ) (ns) 2. default out timing delay is controlled by the txe regist er. by default, this register is set to 1, i.e., two p clock cycles delay or 6666.66 psec. minimum delay can be set to 0. th (ns) tsu (ns) tpw (ns) max min max min max min max min max min sp_clk 3.0 1.4 3.7 3.3 ? ? ? ? ? ? sp_ale 8.5 5.3 9.0 5.4 ? ? ? ? ? ? sp_cs[0] 8.4 5.3 9.0 5.4 ? ? ? ? ? ? sp_cs[1] 8.4 5.3 9.0 5.4 ? ? ? ? ? ? sp_wr 9.1 5.5 9.2 5.6 ? ? ? ? ? ? sp_rd ? ? ? ??????? sp_ack ? ? ? ? 0 0 6.8 4.5 ? ? sp_a[1:0] 8.4 5.3 9.0 5.4 ? ? ? ? ? ? sp_ad[7:0] output to external device 9.0 5.5 9.2 5.6 9.2 5.5 ? ? ? ? sp_ale_l sp_cs_l sp_wr_l sp_ad[7:0] 24:18 17:10 9:2 d[7:0] sp_rd_l a[1:0] sp_a[1:0] [1:0] p_clk 02468 12 14 16 18 20 10 sp_clk t co_fall t co_rise t co t co t co t co t co sp_ack_l t h t su 24:18 17:10 9:2
intel ? IXP2400 network processor 120 datasheet figure 41. mode 0 single read transfer for self-timing device ? slowport table 60. slowport read timing external signals tco rise (default) (ns) tco fall (default) (ns) th (ns) tsu (ns) tpw toz/zo max min max min max min max min max min sp_ale 8.5 5.3 9.0 5.4 ? ? ? ? ? ? ? ? sp_cs[0] 8.4 5.3 9.0 5.4 1 1. the hold cycle can be programmed by sp_rtc1 and sp_rtc2 registers. 2 2. the hold cycle can be programmed by sp_rtc1 and sp_rtc2 registers. sp_cs[1] 8.4 5.3 9.0 5.4 ? ? ? ? ? ? ? ? sp_wr ? ? ? ? 3 3. the pulse width depends on the pulse-width parameter set in the sp_rtc1 and sp_rtc2 registers and the clock di- visor as well. the minimum is 20 ns for one clock cycle at 50 mhz. 4 sp_rd 9.1 5.4 9.2 7.2 ? ? ? ? ? ? ? ? sp_ack ? ? ? ? 0 0 6.8 4.5 ? ? ? ? sp_ad[1:0] 8.4 5.3 9.0 5.4 ? ? ? ? ? ? ? ? sp_ad[7:0] output to external device 9.0 5.5 9.2 5.6 9.2 5.5 ? ? ? ? 7.8 6.0 sp_ad[7:0] input from external device ???? 0 0 7.24.6???? p_clk 02468 12 14 16 18 20 10 sp_ale_l sp_cs_l[1:0] sp_wr_l sp_a[1:0] sp_ad[7:0] sp_ack_l d[7:0] sp_rd_l d[7:0] sp_clk t su t h t co_rise t co_fall t doz t dzo t h t su t h t co t co t co t co t co t h t co 24:18 17:10 9:2 24:18 17:10 9:2
intel ? IXP2400 network processor datasheet 121 4.2.8 jtag 4.2.8.1 jtag dc electrical characteristics 1. all voltages referenced to vss (gnd). 2. ac load current is higher than the shown dc values. 4.2.8.2 jtag ac characteristics 4. the pulse width depends on the pulse-width parameter set in the sp_rtc1 and sp_rtc2 registers and the clock di- visor as well. the minimum is 20 ns for one clock cycle at 50 mhz. table 61. jtag dc specifications symbol parameter conditions minimum maximum unit notes vih input high (logic 1) voltage ? 2.0 vcc3.3 + 0.3 v 1 vil input low (logic 0) voltage ? -0.3 0.8 v ? ili input leakage current output(s) disabled, 0v vin vdd -10.0 +10.0 a ? voh output high voltage ioh = -2.0 ma 2.4 ? v 1, 2 vol output low voltage iol = 2.0 ma 0.4 v 1, 2 vcc3.3 supply voltage ? 3.0 3.6 v 1 figure 42. boundary scan general timing b0540-01 tbscl tbsls tbsoh tbsod tck tms, tdi tdo data in data out tbsch tbsss tbslh tbssh tbsdh tbsdd
intel ? IXP2400 network processor 122 datasheet figure 43. boundary scan tristate timing figure 44. boundary scan reset timing table 62. jtag ac specifications symbol parameter minimum typical maximum unit notes tbscl tck low period 50 ? ? ns ? tbsch tck high period 50 ? ? ns ? tbsis tdi, tms setup to tck 10 ? ? ns ? tbsih tdi, tms hold from tck 10 ? ? ns ? tbsoh tdo hold time 5 ? ? ns 1 tbsod tcf to tdo valid ? ? 40 ns 1 tbsss i/o signal setup to tck 5 ? ? ns 2 tbssh i/o signal hold from tck 20 ? ? ns 2 tbsdh data output hold time 5 ? ? ns 3 tbsdd tcr to data output valid ? ? 40 ns ? tbsoe tdo enable time 5 ? ? ns 1, 4 tbsoz tdo disable time ? ? 40 ns 1, 5 tbsde data output enable time 5 ? ? ns 3, 6 b0541-01 tbscl tbsoe tck tdo tbsch tbsoz tbsde data out tbsdz a9335-01 tbsr ntrst tms tbsrh tbsrs
intel ? IXP2400 network processor datasheet 123 1. assumes a 25 pf load on tdo. output timing derates at 0.072 ns/pf of extra load applied. 2. for correct data latching, the i/o signals (from the core and the pads) must be set up and held with respect to the rising e dge of tck in the capture-dr state of the sample/preload and extest instructions. 3. assumes that the data outputs are loaded with the ac test loads. 4. tdo enable time applies when the tap controller enters the shift-dr or shift-ir states. 5. tdo disable time applies when the tap cont roller leaves the shift-dr or shift-ir states 6. data output enable time applies when the boundary scan logic is used to enable the output drivers. 7. data output disable time applies when the boundary scan logic is used to disable the output drivers. 8. tck may be stopped indefinitely in either the low or high phase. tbsdz data output disable time ? ? 40 ns 3, 7 tbsr reset period 30 ? ? ns tbsrs tms setup to ntrst 10 ? ? ns 8 tbsrh tms hold from ntrst 10 ? ? ns 8 table 62. jtag ac specifications (continued) symbol parameter minimum typical maximum unit notes
intel ? IXP2400 network processor 124 datasheet 5.0 mechanical specifications 5.1 package dimensions the IXP2400 is contained in a 1356 package, as shown in figure 45 . symbols in figure 45 are described in table 63 . figure 45. IXP2400 network processor general mechanical drawing table 63. IXP2400 network processor package dimensions 1356 bga symbol minimum maximum a 3.816 4.46 a1 0.40 0.60 a3 2.266 2.49 b0.61 ref. c 1.15 1.37 b1205-02 s1 e e pin #1 corner a b c d e r g h j k l m n p r t u v w y aa ab ac ad ab af ag ah aj ak al am an ap ar at au s2 e f1 ? b d f2 top view bottom view seating plane side view a3 a c a1 12 3 45 6 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
intel ? IXP2400 network processor datasheet 125 d 37.45 37.55 e 37.45 37.55 f1 33.4 33.6 f2 33.4 33.6 e1.00 s1 0.750 s2 0.750 note: measurements in millimeters. table 63. IXP2400 network processor package dimensions (continued) 1356 bga symbol minimum maximum table 64. IXP2400 network processor die size xyz 17.20 18.67 0.815 note: measurements in millimeters.
126 datasheet this page is intentionally left blank. intel ? IXP2400 network processor

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